EAGER: Design and Exploration of Optical Nanoantenna Technology for Advanced IC Testing and Hardware Security

Sponsor: National Science Foundation (NSF)

Award Number: 1641018

PI: M. Selim Unlu

Co-I/Co-PI: Ajay Joshi

Non-technical: Today’s integrated circuit (IC) chips are used in practically all consumer electronics, as well as in critical defense technologies and municipal support systems such as power and water supply services. To build these chips, state-of-the-art technologies are used that integrate billions of transistors on a single chip. Currently, we do not have the technological know-how for rapid testing of these billion-transistor chips. At the same time, the supply chain and development cycle of IC chips have become increasingly fragmented and global. These two factors, lack of inspection technology and uncertainty in the supply chain, have led to an enormous national security risk. The opportunities for enemies to insert malicious circuitry, termed hardware Trojans, into ICs embedded in critical infrastructure components to tamper with the control and functionality have never been greater. Therefore, there is a pressing need to develop radical and novel solutions for optical testing of current and future technologies and ensure the trustworthiness of ICs. The objective of this research is to explore a completely new paradigm using optical technology based on nanoscopic antennas and the associated measurement techniques that would enable rapid testing, debugging, and securing of IC chips. The expected research outcomes of this project include new knowledge and understanding at the intersection of nanoscale optics, integrated circuits, imaging, and pattern recognition that supports rapid and scalable IC inspection. On the educational front, the PIs plan to actively recruit and support women, under-represented minorities and undergraduate students to participate in this project. This project will provide a multi-disciplinary training environment along with international collaboration exposure for all the students involved in this project.

Technical: Advanced IC technology using 16 nm and 14 nm nodes can integrate billions of transistors on a single chip, thus requiring sub-100 nm optical resolution for isolation of single transistor faults. The proposed research project aims to explore, evaluate and optimize a variety of optical nanoantenna structures and develop methodologies for embedding nanoantennas into the physical layout of individual standard CMOS cells and into the CMOS IC chip as a whole. These nanoantennas will be engineered to direct optical excitation to predetermined chip locations with nanometer accuracy. The interaction of optical excitation with nanoscale devices will be enhanced allowing for testing functional characteristics of ICs with sub-diffraction limited features. Furthermore, the nanoantennas will be designed to elicit unique optical scattering signatures that are highly sensitive to the smallest details of the standard cell geometry. Thus any tampering of the IC through malicious modification of standard cells would be easily detected. The researchers plan to demonstrate this optical watermarking technology in an IC chip designed using a commercial CMOS process. The proposed research will advance knowledge in the integration of optical nanoantennas with ICs, especially related to fabrication compatibility and design approaches as well as their interaction with surrounding circuitry. A successful completion of the proposed research would lead to a paradigm shift in IC chip testing and security.

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