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Title: Hardware Accelerator-based Computing Systems: Interfaces and Taxes

Presenter: Zahra Azad

Advisor: Professor Ajay Joshi (ECE)

Chair: Professor Ayse Coskun (ECE)

Committee: Professor Rabia Yazicigil (ECE)

Abstract: With the end of Dennard scaling near, one of the promising approaches to sustain the historic performance improvement of computing systems is to employ hardware accelerators. As a result, many commercial computing systems integrate one or more accelerators, where each accelerator efficiently executes a specific task. Unfortunately, a realistic system-level end-to-end evaluation of an accelerator, where the accelerator is integrated into a heterogeneous system, reveals that the accelerator benefits are not always as expected. In fact, in some cases the use of a hardware accelerator leads to a performance loss. Hence, we need to decide at run-time when we should use the accelerator and when we should not. To this end, when evaluating the benefits of using a hardware accelerator, we need to consider the full application environment (to determine end-to-end performance) and not only the accelerated portion of the application. Unfortunately, there are no scalable open-source SoC platforms that enable a true evaluation of an accelerator as part of a full system.   In the first part of our research, using AI workloads, we emphasize the need for a holistic, end-to-end analysis of the workloads and discuss the “AI tax” that we need to pay when running AI workloads. Based on our evaluation of a database application, which uses machine learning scoring, running on a heterogeneous system, we found that offloading the inference task to an accelerator is not always beneficial. Moreover, the choice of the optimal hardware backend for inference depends on the input data size, the model complexity, accelerator interface type, and also the hardware resources.   In the second part of our research, we propose a robust and scalable software-hardware framework for accelerator evaluation using an open-source RISC-V based System-on-Chip (SoC) design. Our framework can be used by application/accelerator developers to do an endto-end performance analysis of accelerators by carefully accounting for the interaction of the accelerator with the rest of the system. As part of the future work, we plan to design hardware support for encoding, encryption, and compression operations required for homomorphic encryption in an Internet-of-Things device. We will consider three different designs - a ‘vanilla’ system consisting of a RV64G RISC-V core, an ‘enhanced’ system consisting of RV64G RISCV core + vector ISA extension, and a heterogeneous system consisting of RV64G RISC-V core + hardware accelerators. We plan to prototype all three designs using FPGA and complete an end-to-end evaluation of the three designs to determine the most energy-efficient solution.