2024

  • [NATURE COMM 2024] C. Demirkiran, L. Nair, D. Bunandar, and A. Joshi, “A Blueprint for Precise and Fault-tolerant Analog Neural Networks,” to appear in Nature Communications.
  • [ISCA 2024] C. Demirkiran, G. Yang, D. Bunandar, and A. Joshi, “Mirage: An RNS-Based Photonic Accelerator for DNN Training,” Proc. International Symposium on Computer Architecture (ISCA) 2024. (pdf)
  • [ISCA 2024] R. Agrawal, A. Chandrakasan, and A. Joshi, “HEAP: A Fully Homomorphic Encryption Accelerator with Parallelized Bootstrapping,” Proc. International Symposium on Computer Architecture (ISCA) 2024. (pdf)
  • [ISCA 2024] K. Shivdikar, N. Agostini, M. Jayaweera, G. Jonatan, J. Abellan, A. Joshi, J. Kim, and D. Kaeli, “NeuraChip: Accelerating GNN Computations with a Hash-based Decoupled Spatial Accelerator,” Proc. International Symposium on Computer Architecture (ISCA) 2024. (pdf)
  • [SIGMETRICS 2024] G. Jonatan, H. Cho, H. Son, X. Wu, N. Livesay, E. Mora, K. Shivdikar, J. L. Abellán, A. Joshi, D. Kaeli, and J. Kim, “Scalability Limitations of Processing-in-Memory using Real System Evaluations,” ACM Sigmetric / IFIP Performance, Proc. ACM on Measurement and Analysis of Computing Systems (POMACS) 2024. (pdf)
  • [DATE 2024] C. Rajapaksha, L. Delshadtehrani, R. Muri, M. Egele and A. Joshi, “IOMMU Deferred Invalidation Vulnerability: Exploit and Defense,” in Proc. Design, Automation and Test in Europe (DATE) 2024. (pdf)

2023

  • [MICRO 2023] R. Agrawal, L. Castro, C. Juvekar, A. Chandrakasan, V. Vaikuntanathan, and A. Joshi, “MAD: Memory-Aware Design Techniques for Accelerating Fully Homomorphic Encryption” in Proc. IEEE/ACM International Symposium on Microarchitecture (MICRO) 2023. (pdf)
  • [MICRO 2023] K. Shivdikar, Y. Bao, R. Agrawal, M. Shen, G. Jonatan, E. Mora, A. Ingare, N. Livesay, J. Abellan, J. Kim, A. Joshi, and D. Kaeli, “GME: GPU-based Microarchitectural Extensions to Accelerate Homomorphic Encryption” in Proc. IEEE/ACM International Symposium on Microarchitecture (MICRO) 2023. (pdf)
  • [TVLSI 2023] Z. Azad, G. Yang, R. Agrawal, D. Petrisko, M. Taylor and A. Joshi, “RISE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Encryption,” in IEEE Transactions on Very Large Scale Integration Systems (TVLSI) 2023. (pdf)
  • [JETC 2023] C. Demirkiran, F. Eris, G. Wang, J. Elmhurst, N. Moore, N. Harris, N. Basumallik, V. Reddi, A. Joshi and D. Bunandar, “An Electro-Photonic System for Accelerating Deep Neural Networks,” in ACM Journal on Emerging Technologies in Computing Systems (JETC) 2023. (pdf)
  • [ISLPED 2023] G. Yang, C. Demirkiran, Z. Kizilates, C. Ocampo, A. Coskun, and A. Joshi, “Processing-in-Memory using Optically-Addressed Phase Change Memory,” in Proc. International Symposium on Low Power Electronics and Design (ISLPED) 2023. (pdf)
  • [SNAP-MLSys 2023] C. Demirkiran, R. Agrawal, V. Reddi, D. Bunandar and A. Joshi, “Leveraging Residue Number System for Designing High-Precision Analog Deep Neural Network Accelerators,” in Workshop on Systems for Next-Gen AI Paradigms (SNAP), co-located with Conference on Machine Learning and Systems (MLSys) 2023. (pdf)
  • [SLCA 2023] R. Agrawal and A. Joshi, “Architecting Computing Systems for Fully Homomorphic Encryption,” Synthesis Lectures on Computer Architecture (SLCA) 2023. (link)
  • [IEEE MICRO 2023] N. Livesay, G. Jonatan, E. Mora, K. Shivdikar, R. Agrawal, A Joshi, J. L. Abell ́an, J. Kim, D. Kaeli, “Accelerating Finite Field Arithmetic for Homomorphic Encryption on GPUs,” in Proc. IEEE Micro 2023. (pdf)
  • [HOST 2023] S. Canakci, C. Rajapaksha, A. Nataraja, L. Delshadtehrani, M. Taylor, M. Egele and A. Joshi, “ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance,” in Proc. IEEE International Symposium on Hardware Oriented Security and Trust (HOST) 2023. (pdf) (BEST PAPER AWARD)
  • [DATE 2023] C. Rajapaksha, L. Delshadtehrani, M. Egele and A. Joshi, “SIGFuzz: A Framework for Discovering Microarchitectural Timing Side Channels,” in Proc. Design, Automation and Test in Europe (DATE) 2023. (pdf)
  • [HPCA 2023] R. Agrawal, L. DeCastro, G. Yang, C. Juvekar, R. Yazicigil, A. Chandrakasan, V. Vaikuntanathan and A. Joshi, “FAB: An FPGA-based Accelerator for Bootstrappable Fully Homomorphic Encryption,” in Proc. IEEE International Symposium on High-Performance Computer Architecture (HPCA) 2023. (pdf)

2022

  • [TACO 2022] F. Eris, M. Louis, K. Eris, J. Abellan and A. Joshi, “Puppeteer: A Random Forest-based Manager for Hardware Prefetchers across the Memory Hierarchy,” in ACM Transactions on Architecture and Code Optimization (TACO) 2022. (pdf)
  • [TACO 2022] A. Narayan, Y. Thonnart, P. Vivet, A. Coskun and A. Joshi, “Architecting Optically-Controlled Phase Change Memory,” in ACM Transactions on Architecture and Code Optimization (TACO) 2022. (pdf)
  • [PACT 2022] Y. Bao, Y. Sun, Z. Feric, M. Shen, M. Weston, J. L. Abellán, T. Baruah, J. Kim, A. Joshi and D. Kaeli, “NaviSim: A Highly Accurate GPU Simulator for AMD RDNA GPUs,” in Proc. International Conference on Parallel Architectures and Compilation Techniques (PACT) 2022. (pdf)
  • [SEED 2022] K. Shivdikar, G. Jonatan, E. Mora, N. Livesay, R. Agrawal, A. Joshi, J. L. Abellán, J. Kim and D. Kaeli, “Accelerating Polynomial Multiplication for Homomorphic Encryption on GPUs,” in Proc. IEEE International Symposium on Secure and Private Execution Environment Design (SEED) 2022. (pdf)
  • [HOTCHIPS 2022] N. Harris, D. Bunandar, A. Joshi, A. Basumallik and R. Turner, “Passage: A Wafer-Scale Programmable Photonic Communication Substrate,” in Proc. IEEE Hot Chips Symposium (HCS) 2022. (pdf)
  • [ISLPED 2022] Z. Azad, G. Yang, R. Agrawal, D. Petrisko, M. Taylor and A. Joshi, “RACE: RISC-V SoC for En/decryption ACceleration on the Edge for Homomorphic Computation,” in Proc. International Symposium on Low Power Electronics and Design (ISLPED) 2022. (pdf)
  • [ISMRM 2022] M. Louis, H. Liao, R. Singh, J. Lee, A. Joshi and A. Lin. “Using Machine Learning to Identify Metabolite Spectral Patterns that Reflect Outcome after Cardiac Arrest,” in International Society for Magnetic Resonance in Medicine (ISMRM) Annual Meeting & Exhibition 2022.
  • [ISMRM 2022] M. Louis, H. Liao, A. Joshi and A. Lin. “The Effect of Differences in MRS Parameters on Data Harmonization of Normative Data,” in International Society for Magnetic Resonance in Medicine (ISMRM) Annual Meeting & Exhibition 2022.
  • [ASIACCS 2022] S. Canakci, N. Matyunin, K. Graffi, A. Joshi and M. Egele, “TargetFuzz: Using DARTs to Guide Directed Greybox Fuzzers,” in Proc. ACM ASIA Conference on Computer and Communications Security (ASIACCS) 2022. (pdf)
  • [DATE 2022] P. Das, A. Joshi and H. Kapoor, “Hydra: A Near Hybrid Memory Accelerator for CNN Inference,” in Proc. Design, Automation and Test in Europe (DATE) 2022. (pdf)
  • [SPRINGER 2022] Y. Ma, B. Joardar, P. Pande and A. Joshi, “Interconnect and Integration Technology” to appear in Emerging Computing: From Devices to Systems – Looking Beyond Moore and Von Neumann, Springer Nature 2022.

2021

  • [ACSAC 2021] L. Delshadtehrani, S. Canakci, W. Blair, M. Egele and A. Joshi, “FlexFilt: Towards Flexible Instruction Filtering for Security,” in Proc. Annual Computer Security Applications Conference (ACSAC) 2021. (pdf)
  • [MICRO 2021] J. Ahn, J. Kim, H. Kasan, L. Delshadtehrani, W. Song, A. Joshi and J. Kim, “Network-on-Chip Microarchitecture-based Covert Channel in GPUs,” in Proc. IEEE/ACM International Symposium on Microarchitecture (MICRO) 2021. (pdf)
  • [DAC 2021] S. Canakci, L. Delshadtehrani, F. Eris, M. Taylor, M. Egele and A. Joshi, “DirectFuzz: Automated Test Generation for RTL Designs using Directed Graybox Fuzzing,” in Proc. Design Automation Conference (DAC) 2021. (pdf)
  • [MLArchSys-ISCA 2021] F. Eris, M. Louis, S. Canakci, J. Abellan and A. Joshi, “Custom Tailored Suite of Random Forests for Prefetcher Adaptation,” ML for Computer Architecture and Systems Workshop, co-located with International Symposium on Computer Architecture (ISCA) 2021. (pdf)
  • [ISMRM 2021] M. Louis, E. Coello, H. Liao, A. Joshi and A. Lin, “Quantification of Unsuppressed Water Spectrum using Autoencoder with Feature Fusion,” in International Society for Magnetic Resonance in Medicine (ISMRM) Annual Meeting & Exhibition 2021.
  • [IEEE D&T 2021] B. Zhou. R. Jahanshahi, M. Egele and A. Joshi, “A Cautionary Tale about Detecting Malware Using Hardware Performance Counters and Machine Learning,” in Special Issue of IEEE Design & Test on Hardware Security Top Picks, vol. 38, no. 3, pp. 39-50, June 2021. (pdf)
  • [ISPASS 2021] Z. Azad, R. Sen, K. Park and A. Joshi, “Hardware Acceleration for DBMS Machine Learning Scoring: Is It Worth the Overheads?” in Proc. IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) 2021. (pdf)
  • [ISPASS 2021] M. Buch, Z. Azad, A. Joshi and V. Reddi, “AI Tax in Mobile SoCs: Quantifying the End-to-End AI Application Performance on Smartphones,” in Proc. IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) 2021. (pdf)
  • [ISPASS 2021] T. Baruah, K. Shivdikar, S. Dong, Y.Sun, S. Mojumder, K. Jung, J. Abellán, Y. Ukidave, A. Joshi, J. Kim and D. Kaeli, “GNNMark: A Benchmark Suite to Characterize Graph Neural Network Training on GPUs,” in Proc. IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) 2021. (pdf)
  • [DATE 2021] Y. Ma, L. Delshadtehrani, C. Demirkiran, J. L. Abellan and A. Joshi, “TAP-2.5D: A Thermally-Aware Chiplet Placement Methodology for 2.5D Systems,” in Proc. Design, Automation and Test in Europe (DATE) 2021. (pdf)
  • [DATE 2021] L. Delshadtehrani, S. Canakci, M. Egele and A. Joshi, “SealPK: Sealable Protection Keys for RISC-V,” in Proc. Design, Automation and Test in Europe (DATE) 2021. (pdf)
  • [CRC 2021] A. Narayan, A. Joshi and A. Coskun, “System-Level Management of Silicon-Photonic Networks in 2.5D Systems,” in Silicon Photonics for High Performance Computing and Beyond, CRC 2021.
  • [TCAD 2021] B. Zhou, A. Aksoylar, K. Vigil, R. Adato, J. Tan, B. Goldberg, M. Selim Unlu, and A. Joshi, “Hardware Trojan Detection using Backside Optical Imaging,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 1, pp. 24-37, Jan. 2021. (pdf)

2020

  • [PACT 2020] T. Baruah, Y. Sun, S. Mojumder, J. Abellan, Y. Ukidave, A. Joshi, N. Rubin, J. Kim and D. Kaeli, “Valkyrie: Leveraging Inter-TLB Locality to Enhance GPU Performance,” in Proc. International Conference on Parallel Architectures and Compilation Techniques (PACT) 2020. (pdf)
  • [HPEC 2020] A. Narayan, A. Joshi and A. Coskun, “Bandwidth Allocation in Silicon Photonic Networks using Application Instrumentation,” in Proc. IEEE High Performance Extreme Computing Conference (HPEC) 2020. (pdf)
  • [USENIX-SECURITY 2020] L. Delshadtehrani, S. Canakci, B. Zhou, S. Eldridge, A. Joshi and M. Egele, “PHMon: A Programmable Hardware Monitor and its Security Applications,” in Proc. USENIX Security Symposium 2020. (pdf)
  • [ACCESS 2020] N. Zaraee, B. Zhou, K. Vigil, M. Shahjamali, A. Joshi and M. Selim Unlu, “Gate-level Validation of Integrated Circuits with Structured-Illumination Read-out of Embedded Optical Signatures,” in Proc. IEEE Access, vol. 8, pp. 70900-70912, 2020. (pdf)
  • [IEEE MICRO 2020] D. Petrisko, F. Gilani, M. Wyse, T. Jung, S. Davidson, P. Gao, C. Zhao, Z. Azad, S. Canakci, B. Veluri, T. Guarino, A. Joshi, M. Oskin, and M. Taylor, “BlackParrot: An Agile Open Source RISC-V Multicore for Accelerator SoCs,” IEEE Micro, vol. 40, no. 4, pp. 93-102, 2020. (pdf)
  • [DIMVA 2020] S. Canakci, L. Delshadtehrani, B. Zhou, A. Joshi and M. Egele, “Efficient Context-Sensitive CFI Enforcement through a Hardware Monitor,” in Proc. Conference on Detection of Intrusions and Malware & Vulnerability Assessment (DIMVA) 2020. (pdf)
  • [TCAD 2020] A. Coskun, F. Eris, A. Joshi, A. B. Kahng, Y. Ma*, A. Narayan and V. Srinivas, “Cross-Layer Co-Optimization of Network Design and Chiplet Placement in 2.5D Systems,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 12, pp. 5183-5196, Dec. 2020. (*Lead Author). (pdf)
  • [ISMRM 2020] M. Louis, E. Coello, H. Liao, A. Joshi, and A. Lin, “Quantification of Non-Water-Suppressed Proton Spectroscopy using Deep Neural Networks,” in Proc. International Society for Magnetic Resonance in Medicine (ISMRM) Annual Meeting & Exhibition 2020.
  • [DATE 2020] A. Narayan, Y. Thonnart, P. Vivet, A. Joshi and A. Coskun, “System-level Evaluation of Chip-Scale Silicon-Photonic Networks for Emerging Data-Intensive Applications,” in Proc. Design, Automation and Test in Europe (DATE) 2020. (Invited paper) (pdf)
  • [HPCA 2020] T. Baruah, Y. Sun, A. Dincer, S. Mojumder, J. Abellan, Y. Ukidave, A. Joshi, N. Rubin, J. Kim and D. Kaeli, “Griffin: Hardware-Software Support for Efficient Page Migration in Multi-GPU systems,” in Proc. International Symposium on High-Performance Computer Architecture (HPCA) 2020. (pdf)
  • [BARC 2020] Z. Azad, M. S. Louis, L. Delshadtehrani, A. Ducimo, S. Gupta, P. Warden, V. J. Reddi and A. Joshi, “An End-to-end RISC-V Solution for ML on the Edge Using In-pipeline Support,” in Proc. Boston area ARChitecture (BARC) Workshop 2020. (pdf)
  • [BARC 2020] L. Delshadtehrani, S. Canakci, B. Zhou, S. Eldridge, A. Joshi and M. Egele, “A Programmable Hardware Monitor for Security of RISC-V Processors” in Proc. Boston area ARChitecture (BARC) Workshop 2020. (pdf)
  • [BARC 2020] Z. Azad, S. Canakci, S. Davidson, P. Gao, F. Gilani, T. Guarino, T. Jung, D. Petrisko, B. Veluri, M. Wyse, C. Zhao, M. Oskin, M. Bedford Taylor and A. Joshi, “BlackParrot: An Open-Source RISC-V Multicore Processor A core for and by the world!” in Proc. Boston area ARChitecture (BARC) Workshop 2020.

2019

  • [ISCA 2019] Y. Sun, T. Baruah, S. Mojumder, S. Dong, X. Gong, S. Treadway, Y. Bao, S. Hance, C McCardwell, V. Zhao, H. Barclay, A. Ziabari, Z. Chen, R. Ubal, J. Abellán, J. Kim, A. Joshi and D. Kaeli, “MGPUSim: Enabling Multi-GPU Performance Modeling and Optimization,” in Proc. International Symposium on Computer Architecture (ISCA) 2019. (pdf)
  • [CARRV-ISCA 2019] M. Louis, Z. Azad, L. Delshadtehrani, P. Warden, V. Reddi, S. Gupta and A. Joshi, “Towards Deep Learning using TensorFlow Lite on RISC-V,” in Proc. Workshop on Computer Architecture Research with RISC-V (CARRV) held in conjunction with International Symposium on Computer Architecture (ISCA) 2019. (pdf)
  • [GOMACTECH 2019] Z. Azad, L. Delshadtehrani, F. Gilani, T. Jung, K. Lim, D. Petrisko, M. Wyse, B. Zhou, T. Guarino, B. Veluri, Y. Wang, M. Oskin, A. Joshi, M. Taylor, “The BlackParrot Processor: An Open-Source Industrial-Strength RV64G Multicore Processor,” in Proc. Government Microcircuit Application’s Critical Technology Conference (GOMACTech) 2019.
  • [BARC 2019] B. Zhou, A. Gupta, R. Jahanshahi, M. Egele and A. Joshi, “Can We Reliably Detect Malware Using Hardware Performance Counters?,” in Proc. Boston area ARChitecture (BARC) Workshop 2019. (pdf)
  • [BARC 2019] S. Mojumder, M. Louis, Y. Sun, A. Ziabari, J. Abellan, J. Kim, D. Kaeli and A. Joshi, “Evaluation of Volta-based DGX-1 System Using DNN Workloads,” in Proc. Boston area ARChitecture (BARC) Workshop 2019. (pdf)

2018

  • [ICCAD 2018] A. Coskun, F. Eris*, A. Joshi, A. Kahng, Y. Ma and V. Srinivas, “A Cross-Layer Methodology for Design and Optimization of Networks in 2.5D Systems,” in Proc. International Conference on Computer-Aided Design (ICCAD) 2018. (*Lead Author). (pdf)
  • [IISWC 2018] S. Mojumder, M. Louis, Y. Sun, A. Ziabari, J. Abellan, J. Kim, D. Kaeli and A. Joshi, “Profiling DNN Workloads on a Volta-based DGX-1 System,” in Proc. IEEE International Symposium on Workload Characterization (IISWC) 2018. (pdf)
  • [ISMRM 2018] M. Louis, M. Alosco, B. Rowland, H. Liao, J. Wang, R. Stern, A. Joshi, and A. Lin, “Biomarkers for CTE diagnosis in retired NFL players using Machine learning” in Proc. International Society for Magnetic Resonance in Medicine (ISMRM) Annual Meeting & Exhibition 2018. (pdf)
  • [ASIACCS 2018] B. Zhou, A. Gupta, R. Jahanshahi, M. Egele and A. Joshi, “Hardware Performance Counters Can Detect Malware: Myth or Fact?,” in Proc. ACM Asia Conference on Computer and Communications Security (ASIACCS) 2018. (pdf) (BEST PAPER AWARD)
  • [DATE 2018] F. Eris, A. Joshi, A. Kahng, Y. Ma*, S. Mojumder and T. Zhang, “Leveraging Thermally-Aware Chiplet Organization in 2.5D Systems to Reclaim Dark Silicon,” in Proc. Design, Automation and Test in Europe (DATE) 2018. (*Lead Author). (pdf)
  • [BARC 2018] A. Coskun, F. Eris, A. Joshi, A. Kahng, Y. Ma*, S. Mojumder and T. Zhang, “Reclaiming Dark Silicon Using Thermally-Aware Chiplet Organization in 2.5D Integrated Systems,” in Proc. Boston area ARChitecture (BARC) Workshop 2018. (*Lead Author).
  • [CAL 2018] L. Delshadtehrani, S. Eldridge, S. Canakci, M. Egele and A. Joshi, “Nile: A Programmable Monitoring Coprocessor,” in IEEE Computer Architecture Letters, vol. 17, no. 1, pp. 92-95, 1 Jan.-June 2018. (pdf)

2017

  • [AIPR 2017] M. Louis, M. Alosco, B. Rowland, H. Liao, J. Wang, I. Koerte, M. Shenton, R. Stern, A. Joshi and A. Lin, “Using Machine Learning Techniques for Identification of Chronic Traumatic Encephalopathy Related Spectroscopic Biomarkers,” in Proc. Applied Imagery Pattern Recognition Workshop on Big Data, Analytics and Beyond 2017. (pdf)
  • [HPEC 2017] B. Zhou, M. Egele and A. Joshi, “High-Performance Low-Energy Implementation of Cryptographic Algorithms on a Programmable SoC for IoT Devices,” in IEEE High Performance Extreme Computing Conference 2017. (pdf)
  • [RIVER 2017] T. Zhang, J. Klamkin, A. Joshi and A. Coskun, “Thermal Management of Silicon Photonic NoCs in Many-core Systems,” in Optical Interconnect for Computing Systems, River Publishers 2017. (link)
  • [TCAD 2017] J. Abellán, A. Coskun, A. Gu, W. Jin, A. Joshi, A. Kahng, J. Klamkin, C. Morales, J. Recchio, V. Srinivas and T. Zhang*, “Adaptive Tuning of Photonic Devices in a Photonic NoC Through Dynamic Workload Allocation” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no.5, pp.801-814, May 2017. (*Lead Author) (pdf) 
  • [BARC 2017] L. Delshadtehrani, J. Appavoo, M. Egele, A. Joshi and S. Eldridge, “Varanus: An Infrastructure for Programmable Hardware Monitoring Units,” Proc. Boston area ARChitecture (BARC) Workshop 2017. (pdf)
  • [BARC 2017] Z. Takhirov, J. Wang, V. Saligrama and A. Joshi, “Energy-Efficient Classification: Adaptive Approach,” Proc. Boston area ARChitecture (BARC) Workshop 2017. (pdf)

2016

  • [TACO 2016] A. Ziabari, Y. Sun, Y. Ma, D. Schaa, J. Abellan, R. Ubal, J. Kim, A. Joshi and D. Kaeli, “UMH: A Hardware-based Unified Memory Hierarchy for Systems with Multiple Discrete GPUs,” ACM Transactions on Architecture and Code Optimization vol. 13, no. 4 December 2016. (pdf)
  • [JETC 2016] J. Abellán, C. Chen and A. Joshi, “Electro-Photonic NoC Designs for Kilocore Systems,” ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 13, no. 2, November 2016. (pdf)
  • [ISLPED 2016] Z. Takhirov, J. Wang, V. Saligrama and A. Joshi, “Energy-Efficient Adaptive Classifier Design for Mobile Systems,” Proc. International Symposium on Low Power Electronics and Design (ISLPED) 2016. (pdf)
  • [DATE 2016] A. Coskun, A. Gu*, W. Jin, A. Joshi, A. B. Kahng, J. Klamkin, Y. Ma, J. Recchio*, V. Srinivas* and T. Zhang, “Cross-Layer Floorplan Optimization For Silicon Photonic NoCs In Many-Core Systems”, Proc. Design, Automation and Test in Europe (DATE) 2016. (*Lead Authors) (pdf) 
  • [TVLSI 2016] M. Zangeneh and A. Joshi, “Designing Tunable Sub-threshold Logic Circuits using Adaptive Feedback Equalization” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 3, pp. 884-896, March 2016. (pdf).
  • [BARC 2016] S. Eldridge, T. Unger, M. Louis, A. Waterland, M. Seltzer, J. Appavoo and A. Joshi, “Neural Networks as Function Primitives: Software/Hardware Support with X­FILES/DANA,” Proc. Boston area ARChitecture (BARC) Workshop 2016. (pdf)

2015

  • [PACT 2015] S. Eldridge, A. Waterland, M. Seltzer, J. Appavoo and A. Joshi, “Towards General-Purpose Neural Network Computing,” Proc. Parallel Architectures and Compilation Techniques (PACT) 2015. (pdf)
  • [FIO 2015] R. Adato, A. Uyar, M. Zangeneh, B. Zhou, A. Joshi, B. Goldberg and M. Selim Unlu, “Integrated Nanoantenna Labels for Rapid Security Testing of Semiconductor Circuits,” Proc. Frontiers in Optics 2015.
  • [NOCS 2015] A. Ziabari, J. Abellán, Y. Ma, A. Joshi and D. Kaeli, “Asymmetric NoC Architectures for GPU Systems,” Proc. International Symposium on Networks-on-Chip (NOCS) 2015. (pdf)
  • [DAC 2015] B. Zhou, R. Adato, M. Zangeneh, T. Yang, A. Uyar, B. Goldberg, M. Selim Unlu and A. Joshi, “Detecting Hardware Trojans Using Backside Optical Imaging of Embedded Watermarks,” Proc. Design Automation Conference (DAC) 2015. (pdf)
  • [TCAD 2015] C. Chen, J. Abellán and A. Joshi, “Managing Laser Power in Silicon-Photonic NoC through Cache and NoC Reconfiguration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.34, no.6, pp.972-985, June 2015 (pdf)
  • [ICS 2015] A. Ziabari, J. Abellán, R. Ubal, C. Chen, A. Joshi and D. Kaeli, “Leveraging Silicon-Photonic NoC for Designing Scalable GPUs,” Proc. International Conference on Supercomputing (ICS) 2015. (pdf)
  • [DATE 2015] T. Cilingiroglu, M. Zangeneh, A. Uyar, W. Clem Karl, J. Konrad, A. Joshi, B. Goldberg and M. Selim Unlu, “Dictionary-based Sparse Representation for Resolution Improvement in Laser Voltage Imaging of CMOS Integrated Circuits,” Proc. Design, Automation and Test in Europe (DATE) 2015. (pdf)
  • [BARC 2015] S. Eldridge and A. Joshi, “Exploiting Hidden Layer Modular Redundancy for Fault-Tolerance in Neural Network Accelerators,” Proc. Boston area ARChitecture (BARC) Workshop 2015. (pdf)

2014

  • [NOCS 2014] C. Chen, T. Zhang, P. Contu, J. Klamkin, A. Coskun, and A. Joshi, “Sharing and Placement of On-chip Laser Sources in Silicon-Photonic NoCs,” Proc. International Symposium on Networks-on-Chip (NOCS) 2014. (pdf)
  • [TVLSI 2014] M. Zangeneh and A. Joshi, “Design and Optimization of Nonvolatile Multi-bit 1T1R Resistive RAM,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.22, no.8, pp.1815-1828, Aug. 2014. (pdf)
  • [ALR 2014] F. Raudies, S. Eldridge, A. Joshi and M. Versace, “Learning to navigate in a virtual world using optic flow and stereo disparity signals,” Artificial Life and Robotics, Springer Japan Aug. 2014. (link)
  • [NEUROARCH-ISCA 2014] J. Appavoo, A. Waterland, S. Eldridge, K. Zhao, A. Joshi, S. Homer and M. Seltzer, “Programmable Smart Machines: A Hybrid Neuromorphic approach to General Purpose Computation” Neuromorphic Architectures Workshop (NeuroArch) held in conjunction with 41th International Symposium on Computer Architecture (ISCA-41) 2014. (pdf)
  • [GLSVLSI 2014] S. Eldridge, F. Raudies, D. Zou and A. Joshi, “Neural Network-Based Accelerators for Transcendental Function Approximation,” Proc. Great Lakes Symposium on VLSI (GLSVLSI) 2014. (pdf)
  • [DATE 2014] M. Zangeneh and A. Joshi, “Sub-threshold Logic Circuit Design using Feedback Equalization,” Proc. Design, Automation and Test in Europe (DATE) 2014. (pdf)
  • [DATE 2014] T. Zhang, J. Abellán, A. Joshi and A. Coskun, “Thermal Management of Manycore Systems with Silicon-Photonic Networks,” Proc. Design, Automation and Test in Europe (DATE) 2014. (pdf)
  • [SHAW-HPCA 2014] C. Chen, A. Joshi and E. Salminen, “Profiling EEMBC MultiBench Programs using Full-system Simulations,” Proc. Workshop on SoCs, Heterogeneous Architectures and Workloads (SHAW) held in conjunction with 20th International Symposium On High Performance Computer Architecture (HPCA) 2014. (pdf)

2013

  • [ISLPED 2013] Z. Takhirov, B. Nazer and A. Joshi, “Energy-Efficient Pass-Transistor-Logic Using Decision Feedback Equalization,” Proc. International Symposium on Low Power Electronics and Design (ISLPED) 2013. (pdf)
  • [BIC-ISCA 2013] S. Eldridge, F. Raudies and A. Joshi, “Approximate Computation using Neuralized FPU,” Brain-Inspired Computing (BIC) Workshop held in conjunction with 40th International Symposium on Computer Architecture (ISCA-40) 2013. (pdf)
  • [SPRINGER 2013] C. Batten, A. Joshi, V. Stojanović, and K. Asanović, “Designing Nanophotonic Interconnection Networks,” in Integrated Optical Interconnect Architectures and Applications in Embedded Systems, Springer, 2013. (link)
  • [JSTQE 2013] C. Chen and A. Joshi, “Runtime Management of Laser Power in Silicon-Photonic Multibus NoC Architecture,” IEEE Journal of Selected Topics in Quantum Electronics, vol.19, no.2, pp.338-350, March-April 2013. (Invited paper) (pdf)
  • [BU 2013] F. Raudies, S. Eldridge, A. Joshi and M. Versace, “Reinforcement Learning of Visual Navigation Using Distances Extracted from Stereo Disparity or Optic Flow” (Boston University ECE-2013-1). (pdf)

2012

  • [LGDMA-IGCC 2012] A. Joshi, C. Chen, Z. Takhirov and B. Nazer, “A Multi-layer Approach to Green Computing: Designing Energy-efficient Digital Circuits and Manycore Architectures,” Proc. Workshop on Lighter-than-Green Dependable Multicore Architectures (LGDMA) held in conjunction with International Green Computing Conference (IGCC) 2012. (Invited paper) (pdf)
  • [TVLSI 2012] Z. Wang, M. Karpovsky and A. Joshi, “Nonlinear Multi-Error Correction Codes for Reliable MLC nand Flash Memories,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.20, no.7, pp.1221-1234, July 2012. (pdf)
  • [JETCAS 2012] C. Batten, A. Joshi, V. Stojanovic, and K. Asanovic, “Designing Chip-Level Nanophotonic Interconnection Networks,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol.2, no.2, pp.137-153, June 2012. (pdf)
  • [TVLSI 2012] Z. Wang, M. Karpovsky and A. Joshi, “Secure Multipliers Resilient to Strong Fault-Injection Attacks Using Multilinear Arithmetic Codes,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.20, no.6, pp.1036-1048, June 2012. (pdf)
  • [ICCNS 2012] M. Motter, M. Versace, and A. Joshi, “Neuromorphic solutions for UAS collision avoidance,” Proc. International Conference on Cognitive and Neural Systems (ICCNS) 2012.
  • [GLSVLSI 2012] M. Zangeneh and A. Joshi, “Performance and Energy Models for Memristor-based1T1R RRAM Cell,” Proc. Great Lakes Symposium on VLSI (GLSVLSI) 2012. (pdf)
  • [ISQED 2012] Z. Takhirov, B. Nazer and A. Joshi, “Error Mitigation in Digital Logic using Feedback Equalization with Schmitt Trigger (FEST) Circuit,” Proc. International Symposium on Quality Electronic Design (ISQED) 2012. (pdf)

2011

  • [ALLERTON 2011] Z. Takhirov, B. Nazer and A. Joshi, “A Preliminary Look at Error Avoidance in Digital Logic Via Feedback Equalization,” in Proc. Allerton-11 2011. (Invited paper) (pdf)
  • [HOTI 2011] C. Chen, J. Meng, A. Coskun and A. Joshi, “Express Virtual Channels with Taps (EVC-T): A Flow Control Technique for Network-on-Chip (NoC) in Manycore Systems,”  in Proc. High-Performance Interconnects (HOTI) 2011. (pdf)
  • [GLSVLSI 2011] Z. Wang, M. Karpovsky and A. Joshi, “Influence of Metallic Tubes on the Reliability of CNTFET SRAMs: Error Mechanisms and Countermeasures,” Proc. Great Lakes Symposium on VLSI (GLSVLSI) 2011. (pdf)
  • [GLSVLSI 2011] J. Meng, C. Chen, A. Coskun and A. Joshi, “Run-Time Energy Management of Manycore Systems Through Reconfigurable Interconnects,” Proc. Great Lakes Symposium on VLSI (GLSVLSI) 2011. (pdf)

2010

  • [ISCA 2010] S. Beamer, C. Sun, Y. Kwon, A. Joshi, C. Batten, V. Stojanovic, K. Asanovic, “Re- Architecting a DRAM Memory Channel with Monolithically Integrated Silicon Photonics,” Proc. International Symposium on Computer Architecture (ISCA) 2010 (pdf)
  • [DSN 2010] Z. Wang, M. Karpovsky, A. Joshi, “Reliable MLC NAND Flash Memories Based on nonlinear t-Error-Correcting Codes”, Proc. 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2010 (pdf)
  • [OFC 2010] V. Stojanovic, A. Joshi, C. Batten, Y.-J. Kwon, S. Beamer, S. Chen, and K. Asanovic, “Design-space exploration for CMOS photonic processor networks,” Optical Fiber Communication (OFC), collocated National Fiber Optic Engineers Conference, 2010 Conference on (OFC/NFOEC) , vol., no., pp.1-3, 21-25 March 2010 (pdf)
  • [WTM 2010] V. Stojanovic, A. Joshi, C. Batten, Y.-J. Kwon, S. Beamer, S. Chen and K. Asanovic, “CMOS photonic processor-memory networks,” Photonics Society Winter Topicals Meeting Series (WTM), 2010 IEEE , vol., no., pp.118-119, 11-13 Jan. 2010 (pdf)

2009

  • [ICICSP 2009] Z. Wang, M. Karpovsky, B. Sunar, and A. Joshi, “Design of Reliable and Secure Multipliers by Multilinear Arithmetic Codes,” Proc. Int. Conf. on Information, Communications and Signal Processing, Dec. 2009 (pdf)
  • [UC BERKELEY 2009] S. Beamer, C. Sun, Y. Kwon, A. Joshi, C. Batten, V. Stojanovic and K. Asanovic, “Re-architecting DRAM with Monolithically Integrated Silicon Photonics” (UC Berkeley EECS-2009-179). (pdf)
  • [PICA-MICRO 2009] A. Joshi, C. Batten, Y. Kwon, S. Beamer, I. Shamim, K. Asanovic and V. Stojanovic, “Limits and Opportunities for Designing Manycore Processor-to-Memory Networks using Monolithic Silicon Photonics” Proc. Workshop on Photonic Interconnects & Computer Architecture (PICA) held in conjunction with 42nd Annual ACM/IEEE International Symposium on Microarchitecture, MICRO-42 2009(pdf)
  • [LEOS 2009] A. Joshi, C. Batten, Y.-J. Kwon, S. Beamer, I. Shamim, K. Asanovic and V. Stojanovic, “Designing Manycore Processor Networks using Silicon Photonics,” Proc. IEEE/Photonics Society Annual Meeting 2009. (pdf)

Before September 2009

  • [HOTI 2009] A. Joshi, B. Kim and V. Stojanovic, “Designing Energy-efficient Low-Diameter On-chip Networks with Equalized Interconnects,” Proc. IEEE Symposium on High-Performance Interconnects, Aug 2009. (pdf)
  • [MICRO 2009] C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovic, and K. Asanovic, “Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics,” Micro, IEEE , vol.29, no.4, pp.8-21, July-Aug. 2009. (IEEE Micro Special Issue: Micro’s Top Picks from Hot Interconnects 16) (pdf)
  • [ICS 2009] S. Beamer, K. Asanović, C. Batten, A. Joshi, and V. Stojanović, “Designing Multi-socket Systems Using Silicon Photonics”, Proc. 23rd International Conference on Supercomputing (ICS-09), Yorktown Heights, NY, June 2009. (pdf)
  • [CLEO 2009] V. Stojanovic, A. Joshi, C. Batten, J. Kwon and K. Asanovic, “Manycore Processor Networks with Monolithic Integrated CMOS Photonics,” Proc. CLEO 2009 (Invited paper) (pdf)
  • [NOCS 2009] A. Joshi, F. Chen and V. Stojanovic, “A Modeling and Exploration Framework for Interconnect Network Design in the Nanometer Era,” 3rd IEEE/ACM International Symposium on Network-on-Chip (NOCS-3), May 2009. (pdf)
  • [NOCS 2009] A. Joshi, C. Batten, Y. Kwon, S. Beamer, I. Shamim, K. Asanovic and V. Stojanovic, “Silicon-Photonic Clos Networks for Global On-Chip Communication,” 3rd IEEE/ACM International Symposium on Network-on-Chip (NOCS-3), May 2009 (Nominated for Best Paper Award). (pdf)
  • [HOTI 2008] C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kaertner, R. Ram, V. Stojanovic, and K. Asanovic, “Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics”, Proc. 16th Annual IEEE Symposium on High-Performance Interconnects (Hot Interconnects 2008), Stanford, CA, August 2008. (pdf)
  • [TVLSI 2007] A. Joshi, G. Lopez and J. Davis, “Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.15, no.9, pp.990-1002, Sept. 2007.  (pdf)
  • [NANONETS 2007] F. Chen, A. Joshi, V. Stojanovic and A. Chandrakasan, “Scaling and Evaluation of Carbon Nanotube Interconnects for VLSI Applications,” Proc. Nanonets 2007. (pdf)
  • [IITC 2006] D. Sekar, R. Venkatesan, K. Bowman, A. Joshi, J. Davis and J. Meindl, “Optimal repeaters for sub-50nm interconnect networks,” Proc. IITC 2006, pp. 199-201. (pdf)
  • [VLSI Design 2006] A. Joshi, V. Deodhar and J. Davis, “Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM) Routing,” Proc. VLSI Design 2006, pp. 773-776. (pdf)
  • [TVLSI 2005] A. Joshi and J. Davis, “Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI),” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.13, no.8, pp.899-910, Aug. 2005.  (pdf)
  • [AMC 2005] J. Davis, V. Deodhar and A. Joshi, “The Impact of Wave Pipelining on Future Interconnect Technologies,” Proc. AMC 2005 (Invited paper). (pdf)
  • [SOCC 2005] A. Joshi and J. Davis, “Gigascale ASIC/SoC Design using Wave-Pipelined Multiplexed (WPM) Routing,” Proc. IEEE-SOCC 2005, pp. 139-142. (pdf)
  • [GLSVLSI 2005] A. Joshi and J. Davis, “Wave-Pipelined 2-Slot Time Division Multiplexed (WP/2-TDM) Routing,” Proc. GLSVLSI 2005, pp.446-451. (pdf)
  • [SLIP 2004] A. Joshi and J. Davis, “A 2-Slot Time-Division Multiplexing (TDM) Interconnect Network for Gigascale Integration (GSI),” Proc. IEEE/ACM SLIP Workshop 2004, pp. 64-68. (pdf)

PhD Thesis

  1. Zahra Azad, “On designing hardware accelerator-based systems: interfaces, taxes and benefits,” March 2023.
  2. Rashmi Agrawal, “Hardware accelerators for post-quantum cryptography and fully homomorphic encryption,” November 2022.
  3. Marcia Sahaya Louis, “Machine Learning for Magnetic Resonance Spectroscopy: Modeling in the Pre-clinical Development Process,” June 2022.
  4. Sadullah Canakci, “Directing Greybox Fuzzing to Discover Bugs in Hardware and Software,” March 2022.
  5. Furkan Eris, “Leveraging Machine Learning for Hardware Design and Optimization,” March 2022.
  6. Aditya Narayan, “Energy-efficient architectures for chip-scale networks and memory systems using silicon-photonics technology,” April 2021 (pdf)
  7. Leila Delshadtehrani, “Enabling Software Security Mechanisms Through Architectural Support,” March 2021 (pdf)
  8. Saiful Mojumder, “True Shared Memory Architecture for Next-Generation Multi-GPU Systems,” February 2021 (pdf)
  9. Yenai Ma, “Cross-Layer Design of Thermally-Aware 2.5D Systems,” May 2020. (pdf)
  10. Boyou Zhou, “A Multi-layer Approach to Designing Secure Systems: From Circuit to Software,” March 2019. (pdf)
  11. Zafar Takhirov, “Designing Energy-efficient Computing Systems Using Equalization and Machine Learning,” September 2017. (pdf)
  12. Schuyler Eldridge, “Neural Network Computing using On-chip Accelerators,” August 2016. (pdf)
  13. Mahmoud Zangeneh, “Designing Energy-efficient Sub-threshold Logic Circuits using Equalization and Non-volatile Memory Circuits using Memristors,” March 2015 (pdf)
  14. Chao Chen, “Energy-efficient Electrical and Silicon-photonic Networks in Manycore Systems,” April 2014 (pdf)
  15. Zhen Wang, “Nonlinear Robust Codes and their Applications for Design of Reliable and Secure Devices,” April 2011 (pdf)