BU Computer Systems (BU♺S) Seminar

Join us Thursdays from 12 – 1 pm ET for the BU Computer Systems Seminar

• In Person: Hariri Institute for Computing and Computational Science and Engineering, 665 Commonwealth Ave, Boston, MA, Room 1101 (11th floor)
• Calendar
• Join the Mailing list
• Zoom: https://bostonu.zoom.us/j/96385567387?pwd=azg4M1Y5eXRLcTNqcDlQcU9XOUtIdz09 
  Meeting ID: 963 8556 7387
  Passcode: 195134
• Visit the MOC Alliance YouTube page to view past BU Computer Systems Seminars

The BU Computer Systems Seminar seeks to bring together systems researchers in academia and industry in a forum for discussing design, implementation, analysis and applications of computer systems at various scales. Researchers are invited to present their own work or other significant efforts at the state of the art in operating, distributing, and networking systems and system architectures, of the type typically presented at conferences such as SOSP, OSDI, NDSS, USENIX Security, and NSDI.

Lunch will be provided, when permitted by BU COVID guidelines

Contacts: 
Tara Moran: tmoran@bu.edu
Orran Krieger: okrieg@bu.edu

Schedule

Spring 2024

April 25: Shahin Roozkhosh, Ph.D. Candidate, Boston University, The Devil in the FPGA

• Location (IN-PERSON): Center for Computing & Data Sciences, 665 Commonwealth Ave., Room 1101 (11th floor)
• TIME: 12 – 1 pm ET
• Zoom: https://bostonu.zoom.us/j/96385567387?pwd=azg4M1Y5eXRLcTNqcDlQcU9XOUtIdz09 
  Meeting ID: 963 8556 7387
  Passcode: 195134

• Abstract & Bio

  • Abstract:

    Given the demands of the modern technological landscape, the rate of change in specialized hardware is ever-increasing. However, with the slow-paced and capital-intensive nature of manufacturing, the industry has witnessed the proliferation of heterogeneous systems. Incorporating various processing technologies such as GPUs, NPUs, TPUs, and FPGAs intensifies the need for coherent data sharing across all processing elements. Thus, integrators have to ensure a unified and consistent view of memory between PEs.

    The impact on overall system security remains uncertain. Particularly, the tradeoff for high performance combined with optimized efficiency rather than robust coherence protocols may lead to unknown security vulnerabilities, and this talk emphasizes the extent of such consequences if unaddressed. The gravity of the challenge is recognized, along with the multi-vendors (heterogeneous) acceleration paradigm.

    In this talk, we unveil the potential risks associated with integrating custom hardware into the coherence system. By explaining the underlying hardware coherence support, such as synchronization buses and connectivity infrastructure, we showcase how coherence protocols have overlooked security in favor of high performance. Notably, by acknowledging the necessity to maintain a consistent memory, we highlight the threatening potential for security breaches arising from direct and unsupervised communication.

    Given the quest for flexible deployment offered by systems hosting integrated heterogeneous elements, the physical coherency connections are in place which creates an unexplored hardware threat model. Therefore, the responsibility falls on the software layers to configure and manage these resources effectively. However, the current mechanisms have not been exposed to  for achieving systematic coherence with tightly integrated PEs such as black boxes designed by third parties.

    Motivated by this challenge and multi-vendor trend in modern fabrication, this talk takes the initial steps to study and theorize coherence-based attacks achieved through pragmatic implementation to lay the foundation for the study of counter-measures and emphasize their importance. By introducing a “Coherent Trojan” mimicking the behavior of a cache, we demonstrate how it can practically compromise the CIA triad – Confidentiality, Integrity, and Availability. We will conclude the presentation by examining how a malicious module instantiated in the coherent FPGA, can tamper the execution of a safety-critical task.

  •  Bio:
    Shahin Roozkhosh is a PhD candidate at Boston University (BU), having joined in 2018 under the supervision of Prof. Renato Mancuso. He obtained his master’s degree while pursuing his PhD. Shahin’s research focuses on real-time and embedded systems, with a particular interest in hardware and software co-design on multi-core and partially reconfigurable embedded system-on-chip (SoC) platforms.His work includes practical applications and innovative approaches using on-chip FPGAs, such as coherence-aided routing, spatio-temporal partitioning, cache-bleaching, and on-the-fly tensor acceleration using programmable logic. The latter initiative began during his collaboration with Red Hat, focusing on the development of a relational-memory engine.

    Shahin is committed to both academic and practical applications of his work, aiming for real-world impact through his research endeavors.

April 18: Saad Ullah, Ph.D. Candidate, Boston University, LLMs Cannot Reliably Identify and Reason About Security Vulnerabilities (Yet?): A Comprehensive Evaluation, Framework, and Benchmarks and Ross Mikulskis, Student, Boston University, OPE Gradescope Bridge

• Location (IN-PERSON): Center for Computing & Data Sciences, 665 Commonwealth Ave., Room 1101 (11th floor)
• TIME: 12 – 1 pm ET
• Zoom: https://bostonu.zoom.us/j/96385567387?pwd=azg4M1Y5eXRLcTNqcDlQcU9XOUtIdz09 
  Meeting ID: 963 8556 7387
  Passcode: 195134

• Abstract & Bio

  • LLMs Cannot Reliably Identify and Reason About Security Vulnerabilities (Yet?): A Comprehensive Evaluation, Framework, and Benchmarks
    Abstract: Large Language Models (LLMs) have been suggested for use in automated vulnerability repair, but benchmarks showing they can consistently identify security-related bugs are lacking. We thus develop SecLLMHolmes, a fully automated evaluation framework that performs the most detailed investigation to date on whether LLMs can reliably identify and reason about security-related bugs. We construct a set of 228 code scenarios and analyze eight of the most capable LLMs across eight different investigative dimensions using our framework. Our evaluation shows LLMs provide non-deterministic responses, incorrect and unfaithful reasoning, and perform poorly in real-world scenarios. Most importantly, our findings reveal significant non-robustness in even the most advanced models like `PaLM2′ and `GPT-4′: by merely changing function or variable names, or by the addition of library functions in the source code, these models can yield incorrect answers in 26% and 17% of cases, respectively. These findings demonstrate that further LLM advances are needed before LLMs can be used as general purpose security assistants.Speaker Bio: Saad Ullah is a PhD Candidate in the Electrical and Computer Engineering Department at Boston University, under the guidance of Dr. Gianluca Stringhini. His research focuses on Cybersecurity and Generative AI, with a focus on large language models (LLMs). His aim is to harness LLMs to mimic the reasoning of human experts for efficient handling of programming languages and security tasks. Notably, he has developed SecLLMHolmes, the first automated evaluation framework for assessing the efficiency and reasoning capabilities of LLMs in code security tasks. This tool has also helped identify several critical issues in LLMs, thus enhancing the reliability and trustworthiness of AI-driven programming tools. His ongoing work seeks to create data and resource-efficient solutions that address key challenges in LLMs, such as non-robustness, unfaithful reasoning, and difficulties in analysis of complex code, to improve their applicability in security-centric tasks.
  • OPE Gradescope Bridge
    Abstract: Professors use Gradescope, an academic SaaS, to handle autograding student code assignments; however, the suite of kernels available for running autograder containers is limited. This poses a problem when autograder tests rely on packages that are incompatible with the kernel, and in many cases student submissions may receive lower scores due to test failure. The OPE (Open Education) Bridge uses a lightweight container on Gradescope to invoke a scalable OpenShift service to grade the student submission, and this runs on the same cluster kernel on which the autograder tests are developed. This mode of grading is especially relevant to the Red Hat OPE framework, which provisions standardized cloud containers for students to code their assignments in since everything is centralized on one cluster. Upon completion of grading the student submission, the service sends back the results as JSON, and the Gradescope container publishes it for the student to view. The OPE Bridge allows professors to circumvent grading inaccuracies due to kernel incompatibilities to ensure the most accurate evaluation of student code submissions. This service is currently being used in Orran Krieger’s EC 440 Operating Systems class.Speaker bio: Ross Mikulskis is a 3rd year BA/MS computer science student at Boston University. He has developed testing infrastructure for the Red Hat OPE project with Isaiah Stapleton and is currently using the OPE framework to develop his own free online computer science educational nonprofit, Bits of CS Inc, which has a corresponding free online textbook and has received some funding from Boston University. Ross is very interested in the democratization of education and has relevant experience in teaching, having been a computer science TA for four semesters in CS 330 Algorithms and CS 131 Combinatorics. He hopes to develop solutions for sharing education in an open source, transparent, and collaborative manner to empower underserved communities and incorporate voices from all perspectives.

April 11: Shinan Liu, Ph.D. Candidate, University of Chicago, Operational ML in Networks for Digital Well-being

• Location (IN-PERSON): Center for Computing & Data Sciences, 665 Commonwealth Ave., Room 1101 (11th floor)
• TIME: 12 – 1 pm ET
• Zoom: https://bostonu.zoom.us/j/96385567387?pwd=azg4M1Y5eXRLcTNqcDlQcU9XOUtIdz09 
  Meeting ID: 963 8556 7387
  Passcode: 195134

• Abstract & Bio

  • Abstract:
    The landscape of computer networking has witnessed a rapid expansion, with machine learning (ML) models playing an increasingly vital role in network management, such as service recognition, home network automation, and activity recognition. Operationalizing ML in networking, unlike traditional ML pipelines, presents unique challenges attributable to the specific traits of network data. Factors such as a lack of data sources, the presence of diverse forms of concept drift, and the system’s need to accommodate substantial traffic volumes, all contribute to these complexities. In this talk, I will talk about my recent endeavors on how to effectively solve these challenges, and make ML practical for digital well-being tasks using network information.
  • Bio:
    Shinan Liu is a final year Ph.D. student in the Computer Science Department at the University of Chicago, where he is advised by Prof. Nick Feamster. He earned his Master of Science degree within his Ph.D. program at UChicago in the Summer of 2022 and is a recipient of the Daniels Fellowship. Before his current academic pursuits, he served as the CEO of Chengdu Dominity Co., Ltd., and has gained valuable experience interning at LangSafe.ai, FedML Inc, Virginia Tech, Qihoo 360, Microsoft Research Asia (short-term visit), KnowWhy, and Tsinghua University’s Network Security Lab.He harbors a strong interest in network systems, security, interpretable AI, and measurement, with his research often focusing on cellular networks, the Internet of Things, and cyber-physical systems. His work has been recognized and published in top conferences and journals such as USENIX Security, UbiComp, SIGMETRICS, and CoNext. Additionally, his research has been featured in multiple media outlets, including Forbes, The Wall Street Journal, and ACM TechNews, showcasing its relevance and impact on both the academic community and the general public.

April 4: Denis Hoornaert, Ph.D. Candidate, Technical University of Munich, On-the-fly Reorganization of High-Order Data Objects to Achieve Effortless Locality

• Location (IN-PERSON): Center for Computing & Data Sciences, 665 Commonwealth Ave., Room 1101 (11th floor)
• TIME: 12 – 1 pm ET
• Zoom: https://bostonu.zoom.us/j/96385567387?pwd=azg4M1Y5eXRLcTNqcDlQcU9XOUtIdz09 
  Meeting ID: 963 8556 7387
  Passcode: 195134

• Abstract & Bio

  • Abstract:
    The shift to data-intensive processing from the cloud to the edge has brought new challenges and expectations for the next generation of intelligent computing systems.
    However, a substantial performance gap still exists between the performance of processing elements and sustainable main memory throughput.Modern System-on-Chips heavily rely on multi-level caching architectures to bridge this gap.
    The performance boost provided is often an enabler for adopting data-heavy computation, including machine learning and vision workloads, for live decision-making.
    These caches are most effective for data access patterns that exhibit ideal spatiotemporal locality.
    However, few data-intensive applications are characterized by ideal locality. Instead, when naively implemented, most applications exhibit poor locality and must undergo costly redesigns and tuning to benefit from caching effects.The proposed research tackles the question: Can we leverage application-level knowledge of data access patterns in the underlying memory hierarchy to export ideal data locality?
    In other words, we set our focus on a key limitation of modern computing systems, i.e., that the representation of data in microarchitectural caches mirrors the organization of data in main memory.Our work proposes to investigate the ability to reorganize and reshape the content of data blocks as they are transferred from their representation in main memory to processor-facing caches.
  • Bio:
    Denis Hoornaert (M.Sc) is a Ph.D. student at the Technical University of Munich (TUM, Germany) and a research associate at the Chair of Cyber-physical Systems in Production Engineering (Prof. Marco Caccamo). Previously, he graduated in Computer Science from the Université Libre de Bruxelles (Belgium) in 2019 and collaborated with Hipperos, a Belgian start-up designing real-time operating systems. His current research focuses on the predictability of safety-critical real-time systems.
    In particular, he investigates how hardware/software co-design can help tame memory-originated interference in multi-core System-on-Chips.

February 22—ECE Candidate Seminar: Juncheng Yang, Ph.D. Candidate, Carnegie Mellon University, Designing Efficient and Scalable Cache Management Systems

• Location (IN-PERSON): Center for Computing & Data Sciences, 665 Commonwealth Ave., Room 1750 (17th floor)
• TIME: 11 am – 12pm ET
• Zoom: https://bostonu.zoom.us/j/96385567387?pwd=azg4M1Y5eXRLcTNqcDlQcU9XOUtIdz09 
  Meeting ID: 963 8556 7387
  Passcode: 195134

• Abstract & Bio

  • Abstract:
    Software-managed caches have been ubiquitously deployed in today’s system infrastructure. From personal devices to servers on the edge and the cloud, these caches speed up data access, reduce data movement, and avoid repeated computation. However, they consume a huge amount of resources, i.e., DRAM and CPUsIn this talk, I will discuss how to design efficient and scalable cache systems. In the first part, I will demonstrate that the efficiency of a key-value cache is not only determined by the eviction algorithm but also by other components, e.g., storage layout and expiration design. I will then describe how I designed Segcache to reduce memory footprint by up to 60% and increase throughput by 8x compared to state-of-the-art systems. Segcache has been adopted for production at Twitter and Momento.In the second part, I will introduce a surprising new finding from our largest-scale eviction algorithm study: FIFO queues are all we need for cache eviction. I will then describe S3-FIFO, a new cache eviction algorithm that is simpler, more scalable, and more efficient than state-of-the-art algorithms. S3-FIFO has been adopted for production at Google, VMWare, Redpanda, and several others.Finally, I will describe my future work on building robust, secure, smart, and sustainable data systems.
  • Bio:
    Juncheng Yang (https://junchengyang.com) is a Ph.D. student in the Computer Science Department at Carnegie Mellon University. His research interests broadly cover the efficiency, performance, reliability, and sustainability of large-scale data systems.Juncheng’s works have received best paper awards at NSDI’21, SOSP’21, and SYSTOR’16. His OSDI’20 paper was recognized as one of the best storage papers at the conference and invited to ACM TOS’21.Juncheng received a Facebook Ph.D. Fellowship in 2020, was recognized as a Rising Star in machine learning and systems in 2023, and a Google Cloud Research Innovator in 2023.His work, Segcache, has been adopted for production at Twitter and Momento. The two eviction algorithms he designed (S3-FIFO, SIEVE) have been adopted for production at Google, VMware, Redpanda, and several others with over 20 open-source libraries available on GitHub.

February 15—ECE Candidate Seminar: Konstantinos Kallas, PhD Candidate, University of Pennsylvannia, Programmable Software Systems
for Correct High-Performance Applications

• Location (IN-PERSON): Center for Computing & Data Sciences, 665 Commonwealth Ave., Room 1750 (17th floor)
• TIME: 11 am – 12pm ET
• Zoom: https://bostonu.zoom.us/j/96385567387?pwd=azg4M1Y5eXRLcTNqcDlQcU9XOUtIdz09 
  Meeting ID: 963 8556 7387
  Passcode: 195134

• Abstract & Bio

  • Abstract:
    We live in an era of unprecedented compute availability. The advent of the cloud allows anyone to deploy critical high-performance applications that serve millions of users without owning or managing any computational resources. The goal of my research is to enable the development of such high-performance applications with robust correctness guarantees. To achieve this goal, I build practical programmable software systems that target realistic workloads in widely-used environments. My systems are rooted in solid foundations, incorporating formal specifications and techniques drawn from the programming languages, compilers, and formal methods literature. In this talk I will present some of my work on such systems, including PaSh, the first optimization system for the Unix shell since its inception 50 years ago, as well as MuCache, a caching system for microservice graphs. Surprisingly, the shell and microservices have a key characteristic in common, they are both used to compose black-box components to create applications that are greater than the sum of their parts. I will conclude the talk by arguing that systems research is a key requirement to support the increased compute demands of new applications and enable future breakthroughs.
  • Bio:
    Konstantinos Kallas is a PhD student at the University of Pennsylvania working with Rajeev Alur. He is interested in building systems that enable the development of high-performance applications with robust correctness guarantees, both in theory and in practice. His research has appeared at several venues including OSDI, NSDI, EuroSys, POPL, OOPSLA, and VLDB, and has received the best paper award at EuroSys 21, the best presentation award at HotOS 21, and the 2nd place at the ACM SRC Grand Finals. His research on optimizing shell scripts for parallel and distributed computing environments is supported by the Linux Foundation and part of his research on serverless is incorporated in the Durable Functions framework that is offered by Azure and serves thousands of active users. You can find more information about him on his website: https://www.cis.upenn.edu/~kallas/.

February 8: Daniele Ottaviano, University Federico II of Naples & BU Cyber-Physical Systems Lab | The Omnivisor, The Omnivisor: A real-time static partitioning hypervisor extension for heterogeneous core virtualization over MPSoCs

• Location: Center for Computing & Data Sciences, 665 Commonwealth Ave., Room 1101 (11th floor)
• Zoom: https://bostonu.zoom.us/j/96385567387?pwd=azg4M1Y5eXRLcTNqcDlQcU9XOUtIdz09 
  • Meeting ID: 963 8556 7387
  • Passcode: 195134

• Abstract & Bio

  • Abstract:
    Following the needs of industrial applications, virtualization has been proven to be among the best approaches for the realization of mixed-criticality systems due to the capability of lowering the deployment’s space, weight, power, and cost (SWaP-C). The spread of cutting-edge hardware protection mechanisms for embedded architectures like Multi-Processor Systems on Chip (MPSoCs) opens the door to the development of powerful and highly dependable hypervisors that help developers deal with the complexity of modern technologies while maintaining real-time requirements for critical applications. However, the virtualization support for heterogeneous core clusters over MPSoCs is still overlooked. Modern hypervisors are designed to operate exclusively on main cores, with little or no consideration given to other coprocessors within the system, such as real-time processing units (RPUs) or soft cores deployed on reprogrammable hardware (FPGA). Typically, these coprocessors are regarded as I/O devices allocated to virtual machines that run on primary cores, endowed with full control and responsibility over them. We introduce the Omnivisor, an innovative real-time static partitioning hypervisor model explicitly designed for efficiently managing virtual machines across heterogeneous processing cores within MPSoCs. The Omnivisor addresses the gap by demonstrating that virtual machines can seamlessly operate on cores with different Instruction Set Architectures (ISAs) within the same MPSoC. Moreover, the Omnivisor ensures temporal and spatial isolation between virtual machines by utilizing diverse hardware and software protection mechanisms. The presented approach not only expands the scope of virtualization in MPSoCs, but also enhances the overall system reliability and performance in mixed-criticality applications.

February 1: Kapil Vaidya, Applied Scientist, Amazon Redshift, Sparse Numerical Array-Based Range Filters (SNARF)

• Location: Center for Computing & Data Sciences, 665 Commonwealth Ave., Room 1101 (11th floor)
• Zoom: https://bostonu.zoom.us/j/96385567387?pwd=azg4M1Y5eXRLcTNqcDlQcU9XOUtIdz09 
  • Meeting ID: 963 8556 7387
  • Passcode: 195134

• Abstract & Bio

  • Abstract:
    We present Sparse Numerical Array-Based Range Filters (SNARF),a learned range filter that efficiently supports range queries for numerical data. SNARF creates a model of the data distribution to map the keys into a bit array which is stored in a compressed form. The model along with the compressed bit array which constitutes SNARF are used to answer membership queries. We evaluate SNARF on multiple synthetic and real-world datasets as a stand-alone filter and by integrating it into RocksDB. For range queries, SNARF provides up to 50x better false positive rate than state-of-the-art range filters, such as SuRF and Rosetta, with the same space usage. We also evaluate SNARF in RocksDB as a filter replacement for filtering requests before they access on-disk data structures. For RocksDB, SNARF can improve the execution time of the system up to 10x compared to SuRF and Rosetta for certain read-only workloads.
  • Bio:
    Kapil Vaidya is an Applied Scientist at Amazon Redshift in the Learned Systems Group. He recently graduated from MIT, where he completed his PhD under the guidance of Professor Tim Kraska in the Data Systems Group. His research primarily revolves around the application of machine learning to data systems, with a special focus on the data structures and algorithms integral to these systems. Before that Kapil completed his Bachelors from IIT Bombay.
    

January 25: Collaboratory Student Research Presentations

• Location: Center for Computing & Data Sciences, 665 Commonwealth Ave., Room 1101 (11th floor)
• Zoom: https://bostonu.zoom.us/j/96385567387?pwd=azg4M1Y5eXRLcTNqcDlQcU9XOUtIdz09 
  • Meeting ID: 963 8556 7387
  • Passcode: 195134

• Presentations

  • Presenter: Albert Slepak
    
  • Talk Title: Linux with State Vectors
  • Abstract:

    This project investigates adding efficient Linux support for viewing and manipulating processes as “State Vectors,” a user-accessible, simple binary vector snapshot of values (see background below). This semester’s goal was to exploit the group’s recent RH Collaboratory results in Linux Dynamic Privilege to develop “elevated” State Vector primitives. Using the ability afforded by “elevated” access to directly access kernel data structures and code from a user program (see background below), we explored a primitive we call “ForkU” that can externally clone a running process at various time points, ultimately allowing the creation of a timeline of “doppelganger” processes. Additionally, we explored using “elevated” access to the kernel and hardware virtual memory objects to marshal a process’s address space into a convenient format, such as a JSON file, and later visualize it using web tools. This talk will describe and showcase the challenges, experiences, results, and future works.

    Background: State Vectors: A long-running theme of Professor Appavoo’s lab is using a “State Vector” view of computation. In this view, at each instance of a computation, its registers and memory values are treated as a large binary “State” vector; as the computation proceeds, it traces out a path of State Vectors. The group has exploited this view to explore various ideas, including transparent auto-parallelization (ASC-ASPLOS 2014), exploiting neural network hardware for transparent acceleration (DANA-PACT 2015), and the use of computational caching (Computational Caching SYSTOR ’13) to optimize a Function as a Service platform (SUESS – EUROSys 2020). Dynamic Privilege (Unger 2023): Introduces the ability for a user process to request “elevated” HW privilege, matching that of the OS Kernel. In the elevated state, a process can execute privileged instructions and gain access to the code and data structures of the running OS Kernel. Our Linux prototype offers this ability to authorized binaries via a new system call; “kElevate.”

  • Presenter: Pranet Sharma
    
  • Talk Title: Improving Software Composition Analysis (SCA) Tools with Knowledge Graphs
  • Abstract:
    In this presentation, I will discuss my contribution towards the Red Hat project, Improving Cybersecurity Operations Using Knowledge Graphs. Software Composition Analysis tools allow software developers and security practitioners to identify known security vulnerabilities in open source libraries and ensure supply chain security. These tools scan open-source dependencies present in code to determine if any of the included dependencies have a CVE entry associated with them. There are many different SCA tools available on the market which have different approaches to vulnerability detection and mitigation. Understanding the similarities and differences between the approaches these tools take is essential to determining how Knowledge Graphs can be leveraged to improve their performance. On the basis of qualitative analysis and a case study, various findings are presented.

January 18: Collaboratory Student Research Presentations

• Location: Center for Computing & Data Sciences, 665 Commonwealth Ave., Room 1101 (11th floor)
• Zoom: https://bostonu.zoom.us/j/96385567387?pwd=azg4M1Y5eXRLcTNqcDlQcU9XOUtIdz09 
  • Meeting ID: 963 8556 7387
  • Passcode: 195134

• Presentations

  • Presenters: CJ Para and Patrick Browne
    
  • Talk Title: Exploring Dynamic Off-Loading of Execution to Neural Networks
  • Abstract:
    Our research focuses on determining whether we can use Artificial NeuralNetworks (ANNs) to predict and improve computer program execution based on a
    computer’s low-level machine state. Building on Professor Appavoo’s work on
    Automatically Scalable Computation (ASC) (ASPLOS 2014) and subsequent
    developments like DANA (PACT 2015) and SEUSS (EUROSys 2020), we explore the
    use of modern ML approaches to represent and learn emergent structure from a
    low-level binary representation of a computer systems operation. Specifically,
    we explore the ability of ANNs to learn and predict a system’s future behavior
    by interfacing them with a binary “state vector” representation of the
    computer’s registers and memory. Experimentally, we utilize a simple 6502
    simulator and chess program, along with ANNs implemented on GPUs using
    PyTorch, to conduct a concrete, data-driven study. Our methodology involves
    extensive data collection and training of neural networks, aiming to quantify
    the extent to which low-level operation can reveal meaningful program
    behavior. The methods and infrastructure developed in this work are intended
    to be a foundation for studying if, by exposing a computer program’s execution
    to ML mechanisms, opportunities for accelerations can be automatically
    discovered.

Fall 2023

December 7: Discover Advanced Cloud Technologies

• Location: Center for Computing & Data Sciences, 665 Commonwealth Ave., Room 1101 (11th floor)

• Detailed Agenda

  • Join us on December 7th for a BU Computer Systems Seminar focused on the New England Research Cloud (NERC), complete with lunch provided.  This session, led by Wayne Gilmore, the Executive Director of Research Computing of BU IS&T, and Milson Munakami, the NERC Senior Research Computing Facilitator, will delve into NERC’s comprehensive services, explore its practical use cases, and feature demonstrations of advanced cloud technologies, including RHODS, OpenStack, and OpenShift. Please note that this will be a demonstration-only session without hands-on participation.Detailed Agenda:
    1. In-Depth Look at NERC and Its Core Services:
       • Explore the extensive services offered by NERC, highlighting the account registration process, requesting allocations, and adding people to projects. 
    2. Exploring Real-World Applications:
       • Discussion on various current use cases utilizing NERC, showcasing its practical applications in diverse research fields.
    3. Overview of Key Technologies:
       • RHODS and AI on OpenShift: Introduction to Red Hat OpenShift Data Science (RHODS), a platform for running AI/ML workloads, and Red Hat OpenShift AI, which enables AI application development.
       • OpenStack VMs and OpenShift Containers: Demonstration of how OpenStack VMs and OpenShift Containers facilitate cloud computing and application deployment.
         

    This seminar is a must-attend for those interested in the forefront of cloud computing technologies and their applications in research. We are eager to see you there and engage in a productive discussion.

November 30: Tushar Krishna, Associate Professor, Electrical and Computer Engineering, Georgia Tech, Modeling and Mitigating Communication Bottlenecks for Training and Serving Large AI Models at Scale

• Location: Center for Computing & Data Sciences, 665 Commonwealth Ave., Room 1101 (11th floor)

• Abstract & Bio

  • Abstract:
    The unprecedented success of large language models (LLMs) – such as Open AI’s GPT-3 and GPT-4, Google’s Bard, Meta’s LLaMa , and others – is emphasizing the ever-growing demand to efficiently train them. These models leverage billions to trillions of model parameters and this trend continues to increase at an unforeseen rate. The large model size makes it impossible for their parameters to fit within a single accelerator device, whose memory is usually capped at tens of GBs. Furthermore, even if we succeed to fit the model into a single device, their tremendous compute requirement leads to almost impractical training times. This has led to a growing interest in distributed training, which is the idea of sharding model weights and/or data samples across multiple accelerator devices. However, this comes at the expense of communication overheads to exchange gradients and activations which has already become a key bottleneck for distributed training. The communication challenge is expected to worsen in future systems which are increasingly leveraging multi-dimensional networks with heterogeneous bandwidths due to diverse fabric technologies (e.g., chiplets, rack-scale, and scaleout).
    In this talk, I will present my group’s recent works to address the aforementioned challenges, covering (i) a multi-fidelity simulation framework to study next-generation AI platforms and identify potential bottlenecks, (ii) solutions to co-optimize accelerator hardware and mappings to enhance compute utilization, and (iii) techniques for optimizing communication scheduling to enhance network bandwidth utilization. 
  • Bio:
    Tushar Krishna is an Associate Professor (with tenure) in the School of Electrical and Computer Engineering at Georgia Tech. He is currently also a visiting Associate Professor in the Department of EECS and CSAIL at MIT. He has a Ph.D. in Electrical Engineering and Computer Science from MIT (2014), a M.S.E in Electrical Engineering from Princeton University (2009), and a B.Tech in Electrical Engineering from the Indian Institute of Technology (IIT) Delhi (2007). Dr. Krishna’s research spans computer architecture, interconnection networks, networks-on-chip (NoC), and deep learning accelerators – with a focus on optimizing data movement in modern computing systems. His research is funded via multiple awards from NSF, DARPA, IARPA, SRC (including JUMP2.0), Department of Energy, Intel, Google, Meta/Facebook, Qualcomm and TSMC. His papers have been cited over 14,000 times. Three of his papers have been selected for IEEE Micro’s Top Picks from Computer Architecture, one more received an honorable mention, and four have won best paper awards. Dr. Krishna was inducted into the HPCA Hall of Fame in 2022. He also served as the vice program chair for ISCA 2023.
    

November 16 (Colloquium): Sherard Griffin, Director of Engineering, OpenShift AI, Red Hat, AI Product Strategies and Research Topics

• Location: Center for Computing & Data Sciences, 665 Commonwealth Ave., Room 1101 (11th floor)

• Abstract & Bio

  • Abstract:
    Sherard Griffin will share experiences and strategies for open source AI that work in the real world.  He’ll provide insights into what customers need and how that relates to AI research challenges.
  • Bio:
    Sherard Griffin was responsible for the development of Open Data Hub, a community-driven reference architecture for building and AI-as-a-service platform on OpenShift.  He also leads engineering for Red Hat’s OpenShift AI products and services. 

November 9: Sabrina M. Neuman, Assistant Professor, Computer Science, BU, Designing Computing Systems for Robotics and Physically Embodied Deployments

• Location: Center for Computing & Data Sciences, 665 Commonwealth Ave., Room 1101 (11th floor)

• Abstract & Bio

  • Abstract:
    Emerging applications that interact heavily with the physical world (e.g., robotics, medical devices, the internet of things, augmented and virtual reality, and machine learning on edge devices) present critical challenges for modern computer architecture, including hard real-time constraints, strict power budgets, diverse deployment scenarios, and a critical need for safety, security, and reliability. Hardware acceleration can provide high-performance and energy-efficient computation, but design requirements are shaped by the physical characteristics of the target electrical, biological, or mechanical deployment; external operating conditions; application performance demands; and the constraints of the size, weight, area, and power allocated to onboard computing– leading to a combinatorial explosion of the computing system design space. To address this challenge, I identify common computational patterns shaped by the physical characteristics of the deployment scenario (e.g., geometric constraints, timescales, physics, biometrics), and distill this real-world information into systematic design flows that span the software-hardware system stack, from applications down to circuits. An example of this approach is robomorphic computing: a systematic design methodology that transforms robot morphology into customized accelerator hardware morphology by leveraging physical robot features such as limb topology and joint type to determine parallelism and matrix sparsity patterns in streamlined linear algebra functional units in the accelerator. Using robomorphic computing, we designed an accelerator for a critical bottleneck in robot motion planning and implemented the design on an FPGA for a manipulator arm, demonstrating significant speedups over state-of-the-art CPU and GPU solutions. Taking a broader view, in order to design generalized computing systems for robotics and other physically embodied applications, the traditional computing system stack must be expanded to enable co-design with physical real-world information, and new methodologies are needed to implement designs with minimal user intervention. In this talk, I will discuss my recent work in designing computing systems for robotics, and outline a future of systematic co-design of computing systems with the real world.
  • Bio:
    Sabrina M. Neuman is an Assistant Professor of Computer Science at Boston University. Her research interests are in computer architecture design informed by explicit application-level and domain-specific insights. She is particularly focused on robotics applications because of their heavy computational demands and potential to improve the well-being of individuals in society. She received her S.B., M.Eng., and Ph.D. from MIT, and she was a postdoctoral NSF Computing Innovation Fellow at Harvard University. She is a 2021 EECS Rising Star, and her work on robotics acceleration has received Honorable Mention in IEEE Micro Top Picks 2022 and IEEE Micro Top Picks 2023. She holds the 2023-2026 Boston University Innovation Career Development Professorship.

November 2: Joshua Fried, PhD Student, MIT, Towards Practical Kernel Bypass for Datacenter Computing

• Location: Center for Computing & Data Sciences, 665 Commonwealth Ave., Room 1101 (11th floor)

• Abstract & Bio

  • Abstract:
    Kernel bypass systems have demonstrated that they can significantly improve throughput, latency, and efficiency for I/O intensive datacenter applications relative to traditional operating systems. However, bypassing the kernel has its downsides: it typically requires dedicating resources (e.g. cores, memory) and rewriting applications to use new interfaces. Dedicating resources is undesirable to datacenter operators because these resources may be underutilized as demand shifts over time, and rewriting software is both costly and wastes existing investments in software.In this talk, I will present Junction, a new system that brings the benefits of kernel bypass to unmodified applications, while maintaining a minimal resource footprint for each application. Junction leverages modern network card features to reduce both memory overheads and monitoring overheads, allowing it to pack thousands of instances on one machine. Junction includes a library operating system that provides compatibility with existing applications through an implementation of the Linux system call interface. The implementation embraces kernel bypass to support common OS functionality with minimal reliance on the host kernel. Junction is able to match or exceed the performance of state-of-the-art kernel bypass systems without requiring application porting. Junction delivers improvements in throughput, latency, and CPU efficiency for unmodified network-intensive datacenter applications and supports commonly used frameworks such as Go, Python, and Java without requiring modifications.
  • Bio:
    Joshua Fried is a final year PhD student at MIT advised by Adam Belay. He is broadly interested in operating systems, networks, and distributed systems, with a focus on improving performance and efficiency in datacenters through better operating system design.

October 26: Francesco Restuccia, Postdoctoral Researcher, University of California, San Diego, Do you trust your system interconnect? Toward safe and secure on-chip communications in modern SoCs

• Location: Photonics Building, 8 St. Mary’s st., Boston, MA, Room PHO 210

• Abstract & Bio

  • Abstract:
    Modern system-on-chips (SoCs) are composed of hundreds of heterogeneous hardware modules. The complexity of the modules combined with a strict time-to-market makes full in-house development impractical, pushing SoC vendors to outsource highly specialized third-party modules to external companies. In modern systems, third-party modules have been demonstrated to be a potential source of safety and security threats at the system level, related, for instance, to bus bandwidth stealing, denial-of-service of shared resources, and broken access control. Some of such issues can be attributed to lack of specification in the de-facto standard for on-chip communications on modern SoCs, combined with the specific implementation of the system interconnect. Such issues can be critical in safety- and security-critical applications — automotive, avionics, robotics, medical, space, and cyber-physical system applications are just some examples. This talk provides an overview of our proposed methodologies aiming at enhancing the safety and security of on-chip system communications in modern SoCs. Our solutions mainly rely on three aspects: (i) transparently extending the on-chip interconnect functionalities to enforce the safe and secure operation and interaction of the hardware resources through (a) bandwidth management, (b) access control, (c) prevention of security attacks and fault propagation, and (d) support for dynamic management through hypervisor technologies; (ii) supporting real-time operations and isolation of the modules through novel mathematical analysis bounding the worst-case response times and interference among the modules, and (iii) providing extensive security verification supporting the secure operation of the system. Our solutions have been mainly evaluated in realistic scenarios deployed on modern FPGA SoC platforms. Currently, we are working toward the integration of our methodologies in two popular open-hardware platforms, in a joint effort with academic and industrial partners.
  • Bio:
    Francesco Restuccia is a postdoctoral researcher at the University of California, San Diego. He received his Ph.D. in Computer Engineering (cum laude) from Scuola Superiore Sant’Anna Pisa, Italy, in 2021. He authored and co-authored multiple research articles regarding hardware security, on-chip communications, timing and performance analysis of heterogeneous platforms, and time-predictable hardware acceleration of DNN algorithms. He is co-founder and served as general chair for the first edition of the Safety and Security in Heterogeneous Open System-on-Chip Platforms (SSH-SoC) workshop, held in conjunction with DAC 2023, and served as program co-chair for the 2nd Real-time And intelliGent Edge computing (RAGE) workshop, held in conjunction with CPS-IoT week 2023. He presented his work at multiple academic and industrial venues, most recently at the Qualcomm Product Security Summit 2023 (QPSS 2023).

October 12 (Colloquium): Murat Demirbas, State Machine Replication and the Art of Abstraction

• Location: Photonics Building, 8 St. Mary’s st., Boston, MA, Room PHO 210

• Abstract & Bio

  • Abstract:
    State Machine Replication (SMR) serves as the backbone of dependable distributed systems, including cloud systems at AWS, Meta, Google, Azure, and renowned databases like DynamoDB, Aurora, Spanner, MongoDB, and CockroachDB. SMR ensures replication of operations across nodes as well as their consistent sequencing using Paxos variants for consensus.
    This talk delves into optimizing consensus and refining the SMR abstraction to craft customized high-performance solutions. We spotlight wide-area network and high-throughput SMR solutions, and introduce efficient strategies for performing strongly-consistent reads. We also offer hints for guiding distributed systems design.
  • Bio:
    Murat Demirbas is a Principal Applied Scientist at AWS and a Professor of Computer Science & Engineering at the University at Buffalo, SUNY (on leave).  He developed several influential protocols and systems, including hybrid logical clocks, WPaxos, PigPaxos, and PQR. Murat received a National Science Foundation CAREER award in 2008 and School of Engineering and Applied Sciences Senior Researcher of the Year Award in 2016. He maintains a popular blog on distributed systems at http://muratbuffalo.blogspot.com

October 5: Meet our new PhD students

• Location: 665 Commonwealth Ave, Room 1101, Boston, MA 02215
• Time: 12 – 1 PM ET
• Students: Syed Qasim, Sam Buxbaum, Prateek Jain

September 28: Meet our new PhD students

• Location: 665 Commonwealth Ave, Room 1101, Boston, MA 02215
• Time: 12 – 1 PM ET
• Students:
  • Naima Abrar: https://sites.bu.edu/casp/people/naima-abrar-shami/
  • Shriram Raja: https://www.linkedin.com/in/shriram-raja
  • Eli Baum: https://sites.bu.edu/casp/people/eli-baum/

September 21: Weifan Chen, Low-Overhead Online Assessment of Timely Progress as a System Commodity

• Location: 665 Commonwealth Ave, Room 950, Boston, MA 02215
• Time: 12:15 – 1:15 PM ET

• Abstract & Bio

  • Abstract: The correctness of safety-critical systems depends on both their logical and temporal behavior. Control-flow integrity (CFI) is a well-established and understood technique to safeguard the logical flow of safety-critical applications. But unfortunately, no established methodologies exist for the complementary problem of detecting violations of control flow timeliness. Worse yet, the latter dimension, which we term Timely Progress Integrity (TPI), is increasingly more jeopardized as the complexity of our embedded systems continues to soar. As key resources of the memory hierarchy become shared by several CPUs and accelerators, they become hard-to-analyze performance bottlenecks. And the precise interplay between software and hardware components becomes hard to predict and reason about. How to restore control over timely progress integrity? We postulate that the first stepping stone toward TPI is to develop methodologies for Timely Progress Assessment (TPA). TPA refers to the ability of a system to live-monitor the positive/negative slack – with respect to a known reference – at key milestones throughout an application’s lifespan. In this paper, we propose one such methodology that goes under the name of Milestone-Based Timely Progress Assessment or MB-TPA, for short. Among the key design principles of MB-TPA is the ability to operate on black-box binary executables with near-zero time overhead and implementable on commercial platforms. To prove its feasibility and effectiveness, we propose and evaluate a full-stack implementation called Timely Progress Assessment with 0 Overhead (TPAw0v). We demonstrate its capability in providing live TPA for complex vision applications while introducing less than 0.6% time overhead for applications under test. Finally, we demonstrate one use case where TPA information is used to restore TPI in the presence of temporal interference over shared memory resources.
  • Bio: Weifan’s journey is a bit unconventional. He started out studying physics, then shifted gears into artificial intelligence for his master’s. Now in his third year of a PhD focusing on embedded systems with advisor Renato Mancuso.

September 14: Kinan Albab, K9db: Privacy-Compliant Storage For Web Applications By Construction

• Location: 665 Commonwealth Ave, Room 1101, Boston, MA 02215

• Abstract & Bio

  • Abstract: Data privacy laws like the EU’s GDPR grant users new rights, such as the right to request access to and deletion of their data. Manual compliance with these requests is error-prone and imposes costly burdens especially on smaller organizations, as non-compliance risks steep fines.

    K9db is a new, MySQL-compatible database that complies with privacy laws by construction. The key idea is to make the data ownership and sharing semantics explicit in the storage system. This requires K9db to capture and enforce applications’ complex data ownership and sharing semantics, but in exchange simplifies privacy compliance. Using a small set of schema annotations, K9db infers storage organization, generates procedures for data retrieval and deletion, and reports compliance errors if an application risks violating the GDPR.

    Our K9db prototype successfully expresses the data sharing semantics of real web applications, and guides developers to getting privacy compliance right. K9db also matches or exceeds the performance of existing storage systems, at the cost of a modest increase in state size.

  • Bio: Kinan is a PhD candidate at Brown university advised by Malte Schwarzkopf. Kinan builds systems and tools to improve end user privacy using every tool possible from computer systems, cryptography, and programming languages. His work was cited in the United Nations Guide on Privacy-Enhancing Technologies, and the White House’s National Strategy to Advance Privacy-Preserving Data Sharing and Analytics.  When He is not behind a computer coding, he is probably at a Heavy Metal show, grilling in the backyard, or mixing new cocktails!

September 7: Red Hat Collaboratory – Maximizing Your Proposal Potential Lunch Info Session and Meet-Ups

• Location: 665 Commonwealth Ave, Room 1101, Boston, MA 02215

• More info

  • Red Hat engineers will be present in person at Boston University to discuss research ideas for your 2024 Collaboratory Research Incubation proposals: 
    • Technical and administrative experts will be available for questions and one-on-one meetings
    • 12-1PM: brief presentation and group discussion of RFP, with lunch  
    • 1-4PM: Individual 20-minute focused research discussions (Sign up here)
    • Proposals due: October 2, 2023
  • Additional Information
    • 2024 Request for Proposals (details)
      2023 Grant Awards Announcement 
    • Red Hat Research Project Focus (in progress)

Spring 2023

January 26 (Colloquium): Matthew Miller, Conversation with Fedora Project Leader Matthew Miller

• Location: Center for Computing & Data Sciences, 665 Commonwealth Ave, Room 1101 (11th floor)

• Abstract & Bio

  • Abstract: Join for a conversation about community-driven software development and the future of Linux distributions and related technology — and maybe a little reminiscing about the days of BU Linux (Boston University’s own Fedora-based distro from the early 2000s!)
  • Bio: Matthew Miller is a Distinguished Engineer at Red Hat and is the leader of the Fedora Project, which creates the Fedora Linux distribution.

February 7: Bassel Mabsout, Obtaining Robustness with Reinforcement Learning in Flight Control Systems

• Location: Center for Computing & Data Sciences, 665 Commonwealth Ave, Room 1101 (11th floor)

• Abstract & Bio

  • Abstract:
    In this talk I will mainly be presenting the problems our research group has faced in using Reinforcement Learning (RL) for the purpose of real quadrotor control, and the solutions we have contributed. I will also show how these solutions apply to a general class of robots. Starting from the works of Wil Koch who developed Neuroflight, I will walk through the journey that took us from controllers which would burn the drone’s motors, to controllers beating the standard methods used for such systems, both in performance and power efficiency. In doing so, I will have to talk about the quadrotor’s embedded system, the simulation used for training, the methods used to perform RL, and the way we define robot control intent in these systems. Finally, I will present our more recent results and where we plan to take our research in the future.
  • Bio:

    I am Bassel Mabsout, a computer science PhD student at Boston University. My specializations include Programming Languages, Machine Learning, and Robotics. I aim to utilize the rigorous theoretical tools developed for programming languages, to improve the robustness and compositionality of the state-of-the-art machine learning methods intended for solving difficult control problems. I am presently working with Renato Mancuso (my advisor), Kate Saenko, and Siddharth Mysore on power-efficient and performant attitude control on quadrotors through Reinforcement Learning.

    I am interested in: Type Theory, Metaheuristics, Category Theory, Reinforcement Learning, Agent-Based Models, Control systems, and Differentiable Computation.

February 16: Zongshun Zhang, Towards Optimal Offloading of Deep Learning Tasks

• Location: Center for Computing & Data Sciences, 665 Commonwealth Ave, Room 1101 (11th floor)

• Abstract & Bio

  • Abstract:
    Edge intelligent applications like VR/AR and surveillance have become popular given the growth in IoT devices and mobile devices. However, edge devices with limited capacity cannot support the requirements of increasingly large and complex deep learning (DL) models. To mitigate such challenges, researchers have proposed methods to optimize and offload partitions of DL models among user devices, edge servers, and the cloud. In this setting, each inference task will sequentially pass through all partitions of a model from the user device to the cloud. The classifier at the end of the last partition will make the corresponding predictions. A shortcoming of this method is that the intermediate data transmitted between partitions can be time-consuming to transmit and can reveal information about the source data. To overcome such shortcoming, recent work considers model compression, model distillation, transmission compression, and Early Exits at each partition. The goal is to trade off accuracy with computation delay, transmission delay, and privacy. In this presentation, I will summarize some of the recent developments and future directions in DL task offloading.
  • Bio:
    Zongshun Zhang is a Fourth-year CS Ph.D. student at Boston University, advised by Professor Abraham Matta. His research interests include cloud resource orchestration and edge intelligence systems. He targets using ML(Neural Network) knowledge to enhance performance and save resource costs of Neural Networks deployed at the edge. Presently he is studying the tradeoff among Neural Network accuracy, latency, and resource cost in a hybrid cloud scenario (IaaS v.s. FaaS).

February 23 (Colloquium) POSTPONED: Christina Delimitrou, Designing the Next Generation Cloud Systems: An ML-Driven Approach

• Location: Center for Computing & Data Sciences, 665 Commonwealth Ave, Room 1101 (11th floor)

• Abstract & Bio

  • Abstract:
    
    Cloud systems are experiencing significant shifts both in their hardware, with an increased adoption of heterogeneity, and their software, with the prevalence of microservices and serverless frameworks. These trends require fundamentally rethinking how the cloud system stack should be designed.In this talk, I will briefly describe the challenges these hardware and software trends introduce, and discuss how applying machine learning (ML) to hardware design, cluster management, and performance debugging can improve the cloud’s performance, efficiency, predictability, and ease of use. I will first discuss Dagger, a reconfigurable network accelerator for microservices that shows the advantages of tightly-coupled peripherals, and then present Seer and Sage, two performance debugging systems that leverage ML to identify and resolve the root causes of performance issues in cloud microservices. I will conclude with the open questions that remain for cloud systems, and how ML can help address them.
  • Bio:
    
    Christina Delimitrou is an Assistant Professor at MIT, where she works on computer architecture and computer systems. She focuses on improving the performance, predictability, and resource efficiency of large-scale cloud infrastructures by revisiting the way they are designed and managed. Christina is the recipient of the 2020 TCCA Young Computer Architect Award, an Intel Rising Star Award, a Microsoft Research Faculty Fellowship, an NSF CAREER Award, a Sloan Research Scholarship, two Google Faculty Research Awards, and a Facebook Faculty Research Award. Her work has also received 5 IEEE Micro Top Picks awards and several best paper awards. Before joining MIT, Christina was a professor at Cornell University, and before that, she received her PhD from Stanford University. She had previously earned an MS also from Stanford, and a diploma in Electrical and Computer Engineering from the National Technical University of Athens. More information can be found at: http://people.csail.mit.edu/delimitrou/

March 2: Mert Toslali, Efficient Navigation of Performance Unpredictability in Cloud Through Automated Analytics Systems

• Location: Center for Computing & Data Sciences, 665 Commonwealth Ave, Room 1101 (11th floor)

• Abstract & Bio

  • Abstract:
    The cloud’s performance unpredictability is a significant obstacle to its widespread adoption and can adversely impact costs and revenue. Consequently, engineers strive to diagnose performance-related concerns and deliver high-quality software to enhance performance and meet changing demands. However, the systems employed to diagnose performance necessitate tracing all conceivable application behaviors, incurring substantial overheads. Even after performance issues have been diagnosed and addressed, the current cloud code delivery systems used by engineers lack intelligence, increasing the risk of imprecise decisions and further performance violations.

    
    In this presentation, we will introduce automated, statistically-driven control mechanisms designed to enhance the efficiency and intelligence of diagnosis and code-delivery processes. Firstly, we will demonstrate how dynamically adjusting instrumentation using statistically-driven techniques can optimize instrumentation efficiency. This method enables precise tracing of performance issues while significantly reducing overhead costs. Secondly, we will showcase how an online learning-based approach can intelligently adjust the user traffic split among competing deployments, resulting in minimized performance violations and optimized code-delivery efficiency.
  • Bio:
    Mert Toslali is a 5th year computer engineering PhD student at Boston University. His research is primarily focused on performance diagnosis and online experimentation of cloud applications. He has developed a range of automated, statistically-driven systems that are designed to enhance the performance and efficiency of cloud applications.

March 16 (Colloquium): Adam Belay, MIT, LDB: An Efficient, Full-Program Latency Profiler

• Location: Center for Computing & Data Sciences, 665 Commonwealth Ave, Room 1101 (11th floor)

• Abstract & Bio

  • Abstract:
    Maintaining low tail latency is critical for the efficiency and performance of large-scale datacenter systems. Software bugs that cause tail latency problems, however, are notoriously difficult to debug. In this talk, I will present LDB, a new latency profiling tool that aims to overcome this challenge by precisely identifying the specific functions that are responsible for tail latency anomalies. LDB observes the latency of all functions in a running program. It uses a novel, software-only technique called stack sampling, where a busy-spinning stack scanner thread polls light-weight metadata recorded in call frames, shifting instrumentation cost away from program threads. In addition, LDB records request boundaries and inter-thread synchronization to generate per-request timelines and to find the root cause of complex tail latency problems such as lock contention in multi-threaded programs. Our results show that LDB has low overhead and can rapidly analyze recordings, making it feasible to use in production settings.
  • Bio:
    Adam Belay is an Associate Professor of Computer Science at the Massachusetts Institute of Technology, where he works on operating systems, runtime systems, and distributed systems. During his Ph.D. at Stanford, he developed Dune, a system that safely exposes privileged CPU instructions to userspace; and IX, a dataplane operating system that significantly accelerates I/O performance. Dr. Belay’s current research interests lie in developing systems that cut across hardware and software layers to increase datacenter efficiency and performance. He is a member of the Parallel and Distributed Operating Systems Group, and a recipient of a Google Faculty Award, a Facebook Research Award, and the Stanford Graduate Fellowship. http://abelay.me​

March 23: Yara Awad, BU

• Location: Center for Computing & Data Sciences, 665 Commonwealth Ave, Room 1101 (11th floor)

• Abstract & Bio

  • Bio:
    —–
    I am a PhD candidate in the Department of Computer Science at Boston University, advised by Professor Jonathan Appavoo. My main research falls under operating systems and computer architecture. My broad research agenda targets enabling self-optimization across the spectrum of computation. To that end, one of my goals is to integrate learning mechanisms effectively into a system such that trends in computation may be learned, persisted, retrieved, and shared across computing components. Toward this goal, my current work focuses on the ability to model different subsets of execution in a way that can be consistently learned from and therefore exploited for control and optimization.
  • Abstract:
    ————
    An overarching theme of our lab’s work is to question the ability to affect system change (i.e. control) externally: not from within the system itself, but rather from some control space that is external to the system. We propose that such exogenous control relies on the ability to externally observe relevant system state, learn useful trends as that state mutates, and ultimately discover control policies that can mutate that state in some desired fashion. Our lab’s current work focuses on exogenous energy-aware performance control of a system. In this talk, I will describe the general context of energy-aware performance control and the prior results that motivated our current research direction. These results provide evidence that for some pre-defined network software stack, execution can proceed with optimal energy efficiency when carefully controlled by two hardware-level mechanisms: NIC-level interrupt coalescing, and CPU-level frequency and voltage scaling. Our long-term goals are to 1) prove an innate correlation between these two control settings and the energy profile of a software stack, and 2) exploit this correlation in the face of a real and dynamic network. Our immediate goal is to tackle the constraints posed by the complex nature of network/system interaction which may limit the utility of an exogenous control entity. To that end, I will be presenting different ongoing experiments that we hope can help us answer some open questions: 1) how can a large search space of control decisions be exploited, 2) how can control respond to a dynamic network, and 3) how can control be software-agnostic (i.e. truly external). We propose that when these system-level problems are carefully modeled, machine learning algorithms can help answer these questions.

March 30 (Colloquium): Dionisio de Niz, Carnegie Mellon University: Mixed-Trust Real-Time Computation

• Location: Center for Computing & Data Sciences, 665 Commonwealth Ave, Room 365 (3rd floor)

• Abstract & Bio

  • Bio:

    Dionisio de Niz is a Principal Researcher and the Technical Director of the Assuring Cyber-Physical Systems directorate at the Software Engineering Institute at Carnegie Mellon University. He received a Master of Science in Information Networking and a Ph.D. in Electrical and Computer Engineering both from Carnegie Mellon University. His research interest includes Cyber-Physical Systems, Real-Time Systems, Model-Based Engineering (MBE), and Security of CPS. In the Real-time arena he has recently focused on multicore processors and mixed-criticality scheduling and more recently in real-time mixed-trust computing. In MBE, he has focused on the symbolic integration of analysis using analysis contracts. Dr. de Niz co-edited and co-authored the book “Cyber-Physical Systems” where the authors discuss different application areas of CPS and the different foundational domains including real-time scheduling, logical verification, and CPS security. He has participated and/or helped in the organization of multiple workshops with industry on real-time multicore systems (two co-sponsored by the FAA and three by different services of the US military) and Safety Assurance of Nuclear Energy. He is a member of the executive committee of the IEEE Technical Committee on Real-Time Systems. Dr. de Niz participates regularly in technical program committees of the real-time systems conferences such as RTSS, RTAS, RTCSA, etc. where he also publishes a large part of his work. 

  • Abstract:

    Certification authorities (e.g., FAA) allow the validation of different parts of a system with different degrees of rigor depending on their level of criticality. Formal methods have been recognized as important to verify safety-critical components. Unfortunately, a verified property can be easily compromised if the verified components are not protected from misbehaviors of the unverified ones (e.g., due to bugs). Thus, trust requires that both verification and protection of components are jointly considered. 

    A key challenge to building trust is the complexity of today’s operating systems (OSs) making them impractical to verify. Building a trusted system is challenging because the underlying operating systems (OSs) that implement protection mechanisms are extremely hard (if even possible) to thoroughly verify. Thus, there has been a trend to minimize the trusted computing base (TCB) by developing small verified hypervisors (HVs) and microkernels, e.g., seL4, CertiKOS}, and uberXMHF. In these systems, trusted and untrusted components co-exist on a single hardware platform but in a completely isolated and disjoint manner. We thus call this approach disjoint-trust computing. The fundamental limitation of disjoint-trust computing is that it does not allow the use of untrusted components in critical functionality whose safety must be assured through verification. 

    In this talk, we present the real-time mixed-trust computing (RT-MTC) framework. Unlike disjoint-trust computing, it gives the flexibility to use untrusted components even for CPS critical functionality. In this framework, untrusted components are monitored by verified components ensuring that the output of the untrusted components always lead to safe states (e.g., avoiding crashes). These monitoring components are known as logical enforcers. To ensure trust, these enforcers are protected by a verified micro-hypervisor. To preserve the timing guarantees of the system, RT-MTC uses temporal enforcers, which are small, self-contained codeblocks that perform a default safety action (e.g., hover in a quadrotor) if the untrusted component has not produced a correct output by a specified time. Temporal enforcers are contained within the verified micro-hypervisor. Our framework incorporates two schedulers: (i) a preemptive fixed-priority scheduler in the VM to run the untrusted components and (ii) a non-preemptive fixed-priority scheduler within the HV to run trusted components. To verify the timing correctness of safety-critical applications in our mixed-trust framework, we develop a new task model and schedulability analysis. We also present the design and implementation of a coordination protocol between the two schedulers to preserve the synchronization between the trusted and untrusted components while preventing dependencies that can compromise the trusted component. 

    Finally, we discuss the extension of this framework for trusted mode degradation. While a number of real-time modal models have been proposed, they fail to address the challenges presented here in at least two important respects. First, previous models consider mode transitions as simple task parameter changes without taking into account the computation required by the transition and the synchronization between the modes and the transition. Second, previous work does not address the challenges imposed by the need to preserve safety guarantees during the transition. Our work addresses these issues by extending the RT-MTC framework to include degradation modes and creating a schedulability model based on the digraph model that supports this extension.

April 6: Zeying Zhu, Boston University: Arya: Arbitrary Graph Pattern Mining with Decomposition-Based Sampling 

• Location: Center for Computing & Data Sciences, 665 Commonwealth Ave, Room 1101 (11th floor)

• Abstract & Bio

  • Abstract:
    Graph pattern mining is compute-intensive in processing massive amounts of graph-structured data. This paper presents Arya, an ultra-fast approximate graph pattern miner that can detect and count arbitrary patterns of a graph. Unlike all prior approximation systems, Arya combines novel graph decomposition theory with edge sampling-based approximation to reduce the complexity of mining complex patterns on graphs with up to tens of billions of edges, a scale that was only possible on supercomputers. Arya can run on a single machine or distributed machines with an Error-Latency Profile (ELP) for users to configure the running time of pattern mining tasks based on different error targets. Our evaluation demonstrates that Arya outperforms existing exact and approximate pattern mining solutions by up to five orders of magnitude. Arya supports graphs with 5 billion edges on a single machine and scales to 10-billion-edge graphs on a 32-server testbed.
  • Bio:
    Zeying Zhu is a second-year Ph.D. student at Boston University, advised by Professor Alan Liu. Her research interests are broadly in systems and networking. Specifically, she is interested in programmable networks, monitoring systems, and big data analysis systems with robust algorithm optimizations.

April 27: Tommy Unger, BU: Unikernel Linux (UKL): Building a Unikernel-Aware Linux

• Location: Center for Computing & Data Sciences, 665 Commonwealth Ave, Room 701 (7th floor)

• Abstract & Bio

  • Abstract:
    In this talk, we present our approach to augmenting the Linux kernel, making it compatible with and “aware of” an alternative OS architecture called “Unikernels”. By integrating Unikernels into the Linux environment without disrupting the normal process model, we aim to bridge the gap between the performance advantages of Unikernels and the widespread compatibility of general-purpose operating systems. We will discuss the design of our solution as well as the key observations about Linux that enabled us to add this support in a few hundred lines of code. Through performance results, we quantify some of the benefits of our approach and its potential for driving the widespread adoption of Unikernels.
  • Bio:
    Tommy is a PhD candidate at Boston University with a focus on operating system architecture. His research makes contact with issues of performance, compatibility, and isolation in the context of custom and general purpose operating systems. As he approaches graduation, Tommy continues to challenge conventional beliefs about the application-OS interface, including questioning whether there should be one at all.

May 4 (Colloquium): Joydeep Bannerjee and Randy George, Red Hat: Challenges and opportunities customers have with real-world observability

• Location: Center for Computing & Data Sciences, 665 Commonwealth Ave, Room 1101 (11th floor)

• Abstract & Bio

  • Abstract:
    Red Hat’s Joydeep Banerjee and Randy George combined have decades of experience working with customers and developing monitoring solutions to meet their real-world needs.  In this seminar, they will share what their customers are doing today, their challenges as well as opportunities that they see where academic research could be applied.

May 19: Arne Hamann and Dirk Ziegenbein, Bosch Research: Silverline – A Practical Framework for Building Reliable Distributed System

• Location: Center for Computing & Data Sciences, 665 Commonwealth Ave, Room 1101 (11th floor)

• Abstract & Bio

  • Abstract:
    

    In cooperation with academic partners, Bosch Research is developing the Silverline framework. Silverline follows Bosch’s Reliable Distributed Systems (RDS) vision where safety and real-time critical distributed applications can be executed on top of commercial off-the-shelf (COTS) hardware. If this vision proves successful, it will have a huge impact on today’s HW/SW system architectures. Similar to how music, videos and gaming are already streamed today, it would then also be possible to stream safety and real-time critical functionality from the (edge-)cloud, which would greatly reduce the need for expensive embedded computing power in domains such as automotive or industrial automation.

    This talk explains the motivation behind the design decisions that led to an MVP of the Silverline framework. It also provides some basic insights into the major Silverline components. Finally, Silverline will be shown in action and it will be demonstrated how it can be used to realize flexible and robust edge-based real-time control in industrial automation.

  • Bios:

    Dr. Arne Hamann obtained his PhD in Computer Science in 2008 from the Technical University of Braunschweig Germany. He is Chief Expert for “Distributed Intelligent Systems” at Bosch Research. Like the Bosch product portfolios his range of actives is very broad encompassing complex embedded systems where the interaction between physical processes hardware and software plays a major role through to distributed IoT systems with elements of (edge) cloud computing. In the academic contexts he is member of the editorial board of the ACM journal “Transactions on Cyber Physical Systems” and regularly serves as program committee member for international conferences such as EMSOFT, RTSS, RTAS, DAC, ETFA, and ICCPS.

    Link to Bosch research profile: https://www.bosch.com/research/know-how/research-experts/arne-hamann/

    Dirk Ziegenbein is chief expert for cyber-physical systems engineering and leads a program developing methods and technologies for dynamic distributed systems at Bosch Corporate Research in Stuttgart, Germany. Dirk received a Master’s degree from Virginia Tech and a Ph.D. from Technical University of Braunschweig for his dissertation on modeling and design of embedded systems. He held several positions in R&D (software component technology, scheduling analysis, software architectures for multi-cores, autonomous systems design) and product management (embedded software engineering tools).

May 25 (Colloquium): Roxana Geumbasu, Managing Privacy as a Computing Resource in User-Data Workloads

• Location: Center for Computing & Data Sciences, 665 Commonwealth Ave, Room 1101 (11th floor)

• Abstract & Bio

  • Abstract:

    In this talk, I present the perspective that user privacy should be recognized as a crucial computing resource in user-data workloads and managed accordingly. These workloads, prevalent in today’s companies, constantly compute statistics or train machine learning models on user data, making these “products” of the data available to internal analysts, external partners, and even the general population. However, these products often leak significant information about individual users.  Differential privacy (DP) offers a rigorous way to limit such data leakage by constraining the data products to noisy aggregates.  The talk discusses our group’s work over the past few years on (1) designing a multi-dimensional privacy resource using DP to suit common user-data workloads and (2) integrating support for this resource into popular resource management systems like Kubernetes and caching components. This allows for proper management, including monitoring, scheduling, conservation, payment, and identification of bottlenecks for the privacy resource.  By treating privacy as a computing resource, we put it on par with other computing resources that are routinely managed in computer systems (such as CPU, GPU, and RAM), and we acknowledge that user-data workloads are consuming something extra than just these traditional resources.

    The talk highlights the main lessons I have learned from our experience building these systems. Firstly, considering privacy as a computing resource helps address certain limitations of DP for practical use. Secondly, while DP is close to practical in certain settings, incorporating it into effective systems requires further evolution of DP theory alongside system design. Lastly, I believe the systems research community is uniquely positioned in tackling the remaining challenges of implementing DP in practice, so my talk serves as a call to action for systems researchers to help bring this much needed privacy technology to practice.

  • Bio:

    Roxana Geambasu is an Associate Professor of Computer Science at Columbia University and a member of Columbia’s Data Sciences Institute. She joined Columbia in Fall 2011 after finishing her Ph.D. at the University of Washington.  For her work in data privacy, she received: an Alfred P. Sloan Faculty Fellowship, an NSF CAREER award, a Microsoft Research Faculty Fellowship, several Google Faculty awards, a “Brilliant 10” Popular Science nomination, the Honorable Mention for the 2013 inaugural Dennis M. Ritchie Doctoral Dissertation Award, a William Chan Dissertation Award, two best paper awards at top systems conferences, and the first Google Ph.D. Fellowship in Cloud Computing.